Bit-Slice Processor, 16-Bit, CMOS, CPGA68, CAVITY UP, CERAMIC, PGA-68
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | LOGIC Devices |
| Parts packaging code | PGA |
| package instruction | PGA, |
| Contacts | 68 |
| Reach Compliance Code | unknown |
| ECCN code | 3A001.A.2.C |
| Other features | BYPASS PATH FOR I/O REGISTERS; 2 CONTROL PINS TO SELECT OPERANDS; 3 CONTROL PINS TO SELECT OPERATION |
| maximum clock frequency | 19.23 MHz |
| External data bus width | 16 |
| JESD-30 code | S-CPGA-P68 |
| JESD-609 code | e0 |
| length | 29.464 mm |
| Humidity sensitivity level | 3 |
| Number of terminals | 68 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| Package body material | CERAMIC, METAL-SEALED COFIRED |
| encapsulated code | PGA |
| Package shape | SQUARE |
| Package form | GRID ARRAY |
| Peak Reflow Temperature (Celsius) | 225 |
| Certification status | Not Qualified |
| Maximum seat height | 4.4196 mm |
| Maximum slew rate | 30 mA |
| Maximum supply voltage | 5.5 V |
| Minimum supply voltage | 4.5 V |
| Nominal supply voltage | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | PIN/PEG |
| Terminal pitch | 2.54 mm |
| Terminal location | PERPENDICULAR |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| width | 29.464 mm |
| uPs/uCs/peripheral integrated circuit type | BIT-SLICE MICROPROCESSOR |
| Base Number Matches | 1 |
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