Integrated
Circuit
Systems, Inc.
ICS9159-05
Frequency Generator for Pentium
™
/OPTi VIPER Systems
General Description
The
ICS9159-05
is a low cost frequency generator designed
specifically for Pentium/Pentium Pro systems. The integrated
buffer minimizes skew and provides the early CPU clock required
by some chipsets such as the OPTi VIPER. A 14.318 MHz
XTAL oscillator provides the reference clock to generate
standard Pentium frequencies. The CPU clock makes gradual
frequency transitions without violating the PLL timing of
internal micro-processor clock multipliers.
The synchronous bus frequencies are selectable as CPU for
local bus or CPU/2 for PCI bus support. Green PC systems
are supported through power-down, doze, and glitch-free
stop clock modes.
•
•
•
•
•
•
•
•
Features
Four CPU clocks operate up to 66.6 MHz at 3.3V with
glitch-free start and stop plus smooth transitions
3-6ns early CPU clock supports OPTi VIPER systems
Selection of 6 frequencies, tristate, or power-down
Six BUS clocks support local PCI bus operation
Skew window between synchronous outputs
Integrated buffer outputs drive up to 30pF loads
3.0V - 3.7V supply range
28-pin DIP or 28-pin 300-mil SOIC package
Applications
•
Ideal for green Pentium/Pentium Pro and 486 PCI
systems such as Pentium, PowerPC™ etc.
Block Diagram
Pin Configuration
28-Pin 300-mil SOIC
Pentium is a trademark of Intel Corporaton.
PowerPC is a trademark of Motorola Corporation.
9159-05 Rev F 9/29/98
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any
ICS9159-05
Functionality
Assuming 14.318 MHz input, all frequencies
in MHz. 14 MHz=14.318 MHz
STOP# BSEL#
1
1
1
1
0
0
0
0
0
1
0
1
1
0
0
1
DOZE#
1
1
0
0
1
1
0
0
FS0
X
X
X
X
Select
X
X
X
FS1
X
X
X
X
Select
X
X
X
CPU (0:2)
(MHz)
F
F
F/2
F/2
Stop
Stop
Low
Tristate
ECPU
(MHz)
F
F
F/2
F/2
Run
Stop
Low
Tristate
BUS
(0:5)
(MHz)
F
F
F/4
F/2
Run
Stop
Low
Tristate
FIXED
(MHz)
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
L, L, 14
Tristate
Notes:
1. Where F is Frequency selected by FS (0:1)
2. F value is 66.6, 60, 50 or 33.3.
STOP# BSEL#
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
1
0
1
DOZE#
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
FS0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Select
2
Select
2
Select
2
X
X
X
FS1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Select
2
Select
2
Select
2
X
X
X
CPU (0:2)
(MHz)
66.6
60
50
33.3
66.6
60
50
33.3
33.3
30
25
16.7
33.3
30
25
16.7
F
3
F/2
Stop
Stop
Low
Tristate
ECPU
(MHz)
66.6
60
50
33.3
66.6
60
50
33.3
33.3
30
25
16.7
33.3
30
25
16.7
F
3
F/2
Run
Stop
Low
Tristate
BUS
(0:5)
(MHz)
33.3
30
25
16.7
66.6
60
50
33.3
16.7
15
12.5
8.3
33.3
30
25
16.7
F
3
F/2
Run
Stop
Low
Tristate
FIXED
(MHz)
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
24, 12, 14
L, L, 14
L, L, 14
Tristate
Notes:
1. 000 mode powers-down the PLL sections and forces the outputs low. To ensure glitch-free start and
stop of the CPU and BUS clocks, enter 000 from 001 and exit 000 through 001.
2. Select is FS0, Fs1 = 00, 01, 10, 11.
3. F is the value of CPU, ECPU & BUS. F value is 66.6, 60, 50 or 33.3 as selected by FS(0:1).
2
ICS9159-05
Pin Descriptions
PIN
NUMBER
8, 20, 26
1
2
3, 11, 23, 17
6, 7, 9
4, 5
10
15, 16, 18,
19,21, 22
12
13
14
24
25
27, 28
PIN NAME
VDD
X1
X2
GND
CPU(0:2)
FS(0:1)
ECPU
BUS(0:5)
DOZE#
BSEL#
1
TYPE
PWR
IN
OUT
PWR
OUT
IN
OUT
OUT
IN
IN
DESCRIPTION
Power for logic, CPU and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 4-20 MHz XTAL, normally 14.318 MHz.
XTAL output which includes XTAL load capacitance.
Ground for logic, CPU and fixed frequency output buffers.
Processor clock outputs which are a multiple of the input reference frequency as
shown in the table.
Frequency multiplier select pins. See table below. These inputs have internal pull-
up devices.
Early CPU clock. Transition precedes CPU clocks.
Bus clock outputs are fixed at 1/2 the PCLK frequency.
Doze mode control. Reduces CPU and BUS clock frequencies by 1/2 when low.
BUS select for BSEL = 0, BUS = CPU/2
for BSEL = 1, BUS = CPU
Stop Clock. Stops all CPU clock outputs and forces them to a logic low level
synchronously with their next low level transition.
12 MHz fixed clock (with 14.318 MHz input).
24 MHz fixed clock (with 14.318 MHz input).
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
1
1
STOP#
KEYBD
DISK
REF (0:1)
OUT
OUT
OUT
Note:
1. Internally pulled-up
3
ICS9159-05
Absolute Maximum Ratings
Supply Voltage .......................................................................................................... 7.0 V
Logic Inputs ....................................................................... GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature ............................................................. 0°C to +70°C
Storage Temperature ........................................................................... –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics at 3.3V
V
DD
= 3.0 – 3.7 V, T
A
= 0 – 70
°
C unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Current
1
Output High Current
1
Output Low Current
1
Output High Current
1
Output Low Voltage
1
Output High Voltage
1
Output Low Voltage
1
Output High Voltage
1
SYMBOL
V
IL
V
IH
I
IL
I
IH
I
OL
I
OH
I
OL
I
OH
V
OL
V
OH
V
OL
V
OH
I
DD
Supply Current
I
DDPD
I
DDS
V
IN
=0V
V
IN
=V
DD
V
OL
=0.8V; for CPU & BUS
V
OL
=2.0V; for CPU & BUS
V
OL
=0.8V; for fixed CLKs
V
OL
=2.0V; for fixed CLKs
I
OL
=15mA; for CPU & BUS
I
OH
=-30mA; for CPU & BUS
I
OL
=12.5mA; for fixed CLKs
I
OH
=-20mA; for fixed CLKs
@ 66.6 MHz; all outputs
unloaded
@ 000 mode (power-down)
@ 001 mode (stop)
TEST CONDITIONS
MIN
-
0.7V
DD
-25.0
-5.0
30.0
-
25.0
-
-
2.4
-
2.4
-
TYP
-
-
-5
-
47.0
-66.0
38.0
-47.0
0.30
2.8
0.30
2.8
55
8
35
MAX
0.2V
DD
-
-
5.0
-
-42.0
-
-30.0
.4
-
.4
-
110
20
70
V
mA
a
a
UNITS
V
V
µA
µA
mA
mA
mA
mA
V
V
Note 1:
Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS9159-05
Electrical Characteristics at 3.3V
V
DD
= 3.0 – 3.7 V, T
A
= 0 – 70
°
C unless otherwise stated
AC Characteristics
PARAMETER
Rise Time
1
Fall Time
1
Rise Time
1
Fall Time
1
Duty Cycle
1
Jitter, One Sigma
1
Jitter, Absolute
1
Jitter, One Sigma
1
Jitter, Absolute
1
Input Frequency
1
Logic Input Capacitance
1
Crystal Oscillator Capacitance
1
Clock Skew Window
1
Clock Skew Window
1
Clock Skew Window
1
Clock Skew Window
1
SYMBOL
T
r1
T
f1
T
r2
T
f2
D
t
T
j1s1
T
jab1
T
j1s2
T
jab2
F
i
C
IN
C
INX
T
sk1
T
sk
T
sk3
T
SR4
Logic input pins
X1, X2 pins
CPU to CPU; Load=20pF; @1.4V
BUS to BUS;
Load=20pF @1.4V
ECPU to CPU;
Load=20pF; @1.4V
CPU to BUS;
Load=20pF; @1.4v
TEST CONDITIONS
20pF load, 0.8 to 2.0V
CPU & BUS
20pF load, 2.0 to 0.8V
CPU & BUS
20pF load, 20% to 80%
CPU & BUS
20pF load, 80% to 20%
CPU & BUS
20pF load @ V
O U T
=1.4V
CPU & BUS Clocks; Load=20pF,
R
S
=33
Ω
CPU & BUS Clocks; Load=20pF,
R
S
=33
Ω
Fixed CLK; Load=20pF
Fixed CLK; Load=20pF
MIN
-
-
-
-
45
-
-300
-
-
4.0
-
-
-
-
3.0
0.5
TYP
0.9
0.8
1.5
1.4
50
40
-
1
2
14.318
5
18
150
300
-
1.0
MAX
1.5
1.4
2.5
2.4
55
150
300
3
5
20.0
-
-
250
500
6.0
3.0
UNITS
ns
ns
ns
ns
%
ps
ps
%
%
MHz
pF
pF
ps
ps
ns
ns
Note 1:
Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
Sensor
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