ICS85301AGLF datasheet, PDF - EEWORLD Datasheet

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ICS85301AGLF: Description85301 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16; Categorysemiconductor logic; File Size292KB，19 Pages; ManufacturerICS ( IDT ); Websitehttp://www.icst.com

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ICS85301AGLF Overview

85301 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

ICS85301AGLF Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	2.62 V
Minimum supply/operating voltage	2.38 V
Rated supply voltage	2.5 V
Processing package description	4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
state	TRANSFERRED
packaging shape	RECTANGULAR
Package Size	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.6500 mm
terminal coating	TIN LEAD
Terminal location	DUAL
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
series	85301
Enter conditions	DIFFERENTIAL MUX
Logic IC type	LOW SKEW CLOCK DRIVER
Number of inverted outputs	0.0
Real output number	1
propagation delay TPD	0.4900 ns

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Integrated

Circuit

Systems, Inc.

ICS85301

2:1

IFFERENTIAL

-LVPECL M

ULTIPLEXER

EATURES

•

2:1 LVPECL MUX

•

One LVPECL output

•

Two differential clock inputs can accept: LVPECL, LVDS,

CML

•

Maximum input/output frequency: 3GHz

•

Translates LVCMOS/LVTTL input signals to LVPECL levels

by using a resistor bias network on nPCLK0, nPCLK0

•

Propagation delay: 490ps (maximum)

•

Part-to-part skew: 150ps (maximum)

•

Additive phase jitter, RMS: 0.009ps (typical)

•

Full 3.3V or 2.5V operating supply

•

-40°C to 85°C ambient operating temperature

•

Available in both standard and lead-free RoHS compliant

packages

ENERAL

ESCRIPTION

The ICS85301 is a high performance 2:1 Differ-

ential-to-LVPECL Multiplexer and a member of the

HiPerClockS™

HiPerClockS™ family of High Performance Clock

Solutions from ICS. The ICS85301 can also per-

form differential translation because the differ-

ential inputs accept LVPECL, CML as well as LVDS levels.

The ICS85301 is packaged in a small 3mm x 3mm

16 VFQFN package, making it ideal for use on space con-

strained boards.

LOCK

IAGRAM

PCLK0

nPCLK0

PCLK1

nPCLK1

SSIGNMENT

PCLK0 1

nPCLK0 2

PCLK1 3

nPCLK1 4

16 15 14 13

CLK_SEL

ICS85301

16-Lead VFQFN

3mm x 3mm x 0.95 package body

K Package

Top View

PCLK0

nPCLK0

PCLK1

nPCLK1

CLK_SEL

ICS85301

16-Lead TSSOP

4.4mm x 5.0mm x 0.92mm

package body

G Package

Top View

85301AK

www.icst.com/products/hiperclocks.html

REV. A JANUARY 16, 2006

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