HV510
240V, 12-Channel Serial to Parallel Converter
with High Voltage Push-Pull Outputs
Ordering Information
Package Options
Device
HV510
Recommended Operating
V
PP
Max
240V
24 Lead SOW
HV510WG
Die
HV510X
Features
❏
HVCMOS
®
technology
❏
Operating output voltage of 240V
❏
Low power level shifting from 5V to 240V
❏
Shift register speed 8MHz @ V
DD
= 5V
❏
12 latched data outputs
❏
Output polarity and blanking
❏
CMOS compatible inputs
❏
Forward and reverse shifting options
General Description
The HV510 is a low voltage serial to high voltage parallel con-
verter with 12 high voltage push-pull outputs. This device has
been designed to drive small capacitive loads such as piezo
electric transducers. It can also be used in any application
requiring multiple high voltage outputs, low current sourcing and
sinking capabilities.
The device consists of a 12-bit shift register, 12 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through the
device. With DIR grounded, D
IOA
is Data In and D
IOB
is Data Out;
data is shifted from HV
OUT
12 to HV
OUT
1. When DIR is at logic high,
D
IOB
is Data In and D
IOA
is Data Out: data is then shifted from
HV
OUT
1 to HV
OUT
12. Data is shifted through the shift register on
the low to high transition of the clock. Data output buffers are
provided for cascading devices. Operation of the shift register is
not affected by the LE, BL, or the POL inputs. Transfer of data from
the shift register to the latch occurs when the LE is high. The data
in the latch is stored during LE transition from high to low.
Absolute Maximum Ratings
1
Supply voltage, V
DD
Supply voltage, V
PP
Logic input levels
Ground current
3
High voltage supply current
2
Continuous total power dissipation
3
Operating temperature range
Storage temperature range
-0.5V to +6V
V
DD
to 260V
-0.5V to V
DD
+0.5V
0.3A
0.25A
750mW
-40°C to +85°C
-65°C to +150°C
Notes:
1. All voltages are referenced to GND.
2. Connection to all power and ground pads is required. Duty cycle is limited by
the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to 85°C at 12mW/°C.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
1
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV510
Electrical Characteristics
(for V
DC Characteristics
Symbol
I
DD
I
DDQ
I
PP
I
IH
I
IL
V
OH
Parameter
V
DD
supply current
Quiescent V
DD
supply current
High voltage supply current
DD
= 5V, V
PP
= 240V, T
A
= 25
0
C)
Min
Typ
Max
4
Units
mA
Conditions
f
CLK
= 8MHz, f
DATA
= 4MHz
LE = LOW
200
0.25
0.25
µA
mA
mA
µA
µA
V
V
V
25
1.0
V
PP
+1.5
-1.5
1.0
0.8
V
V
V
V
mA
mA
All V
IN
= 0V or V
DD
V
PP
= 240V All outputs high
V
PP
= 240V All outputs low
V
IH
= V
DD
V
IL
= 0V
V
PP
= 240V, IHV
OUT
= -0.5mA
V
PP
= 200V, lHV
OUT
= -0.5mA
I
DOUT
= -100µA
V
DD
= 5V, IHV
OUT
= 1mA
I
DOUT
= 100µA
I
OL
= 1mA
I
OL
= -1mA
V
PP
= 240V
V
PP
= 200V
High-level logic input current
Low-level logic input current
High-level output
HV
OUT
Data out
220
175
V
DD
-1V
10
-10
V
OL
V
OC
I
OH
Low-level output
HV
OUT
Data out
HV
OUT
clamp voltage
Output Source Current
AC Characteristics
1
(For V
DD
= 5V, V
PP
= 200V, T
A
= 25°C)
Symbol
f
CLK
t
W
t
SU
t
H
t
WLE
t
DLE
t
SLE
t
ON
, t
OFF
t
DHL
t
DLH
t
r
, t
f
Clock frequency
Clock width high and low
Data setup time before clock rises
Data hold time after clock rises
Width of latch enable pulse
LE delay time after rising edge of clock
LE setup time before rising edge of clock
Time from latch enable to HV
OUT
Delay time clock to data out high to low
Delay time clock to data out low to high
All logic inputs
62
35
30
80
35
40
6.0
125
125
5
Parameter
Min
Typ
Max
8
Units
MHz
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
C
L
= 20pF
C
L
= 20pF
C
L
= 20pF
Conditions
Note:
1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec.
Recommended Operating Conditions
Symbol
V
DD
V
PP
V
IH
V
IL
T
A
Logic supply voltage
High voltage supply
High-level input voltage
Low-level input voltage
Operating free-air temperature
Parameter
Min
4.5
60
V
DD
-0.9
0
-40
Typ
5.0
Max
5.5
240
V
DD
0.9
+85
Units
V
V
V
V
°C
Notes:
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
Power-down sequence should be the reverse of the above.
4.
5.
Apply V
PP
.
The V
PP
should not drop below V
DD
or float during operation.
2
PCB Design
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