ZL30791, ZL30795, ZL30793
IEEE 1588 & Synchronous Ethernet
Packet Clock Network Synchronizers
Product Brief
August 2019
Features
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One, Two or Three DPLL Channels
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Packet and/or physical-layer frequency, phase
and time synchronization
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Physical-layer compliance with ITU-T G.8262,
G.8262.1, G.813, G.812, Telcordia GR-1244,
GR-253
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Packet-timing compliance with ITU-T G.8261,
G.8263, G.8273.2 (class A,B,C&D), G.8273.4
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Enables 5G wireless applications with sub-
100ns time/phase alignment requirements
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Programmable bandwidth, 0.1mHz to 470Hz
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Hitless reference switching and mode switching
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High-resolution holdover averaging
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Programmable phase slope limit for transients,
downto 1 ns/s
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Per-DPLL phase adjustment, 1ps resolution
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Input Clocks
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Accepts up to 10 differential or CMOS inputs
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Any input frequency from 0.5Hz to 900MHz
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Per-input activity and frequency monitoring
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Automatic or manual reference switching
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Fast lock to 1 PPS input, <30 seconds
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Any input can be a 1PPS SYNC input for
REF+SYNC frequency/phase/time locking
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Any input can be a clock with embedded 1PPS
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Per-input phase adjustment, 1ps resolution
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Output Clock Frequency Generation
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Any output frequency from <0.5Hz to 1045MHz
(180MHz max for Synth0)
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High-resolution fractional frequency conversion
with 0ppm error
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Synthesizers 1 & 2 have integer and fractional
dividers to make a total of 5 frequency families
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Output jitter from Synths 1 & 2 is <0.3ps RMS
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Output jitter from fractional dividers is typically
< 1ps RMS, many frequencies <0.5ps RMS
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Each HPOUTP/N pair can be LVDS, LVPECL,
HCSL, 2xCMOS, HSTL or programable diff.
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Four output banks each with VDDO pin; CMOS
output voltages from 1.5V to 3.3V
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Per-synthesizer phase adjust, 1ps resolution
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Ordering Information
ZL30791LFG7
ZL30795LFG7
ZL30793LFG7
1-Channel
2-Channel
3-Channel
80-lead LGA Trays
80-lead LGA Trays
80-lead LGA Trays
NiAu (Pb-free)
Package size: 11 x 11 mm
-40
C to +85
C
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Per-output programmable duty cycle
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Precise output alignment circuitry and per-
output phase adjustment
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Per-output enable/disable and glitchless
start/stop (stop high or low)
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Local Oscillator
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Operates from a single TCXO or OCXO: 23.75-
25MHz, 47.5-50MHz, 114.285-125MHz
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Very-low-jitter applications can connect a TCXO
or OCXO as the stability reference and a low-
jitter XO as the jitter reference
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General Features
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Automatic self-configuration at power-up from
internal Flash memory
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Input-to-output alignment <2ns
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Internal compensation (1ppt) for local oscillator
frequency error in DPLLs and input monitors
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Numerically controlled oscillator behavior in
each DPLL and each fractional output divider
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Programmable Time of Day counters
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Easy-to-configure design requires no external
VCXO or loop filter components
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7 GPIO pins with many possible behaviors
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SPI or I
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C processor Interface
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1.8V and 3.3V core VDD voltages
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Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out
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Easy-to-use evaluation/programming software
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Factory programmable power-up configuration
Applications
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Central system timing ICs for SyncE and/or
IEEE 1588, SONET/SDH, OTN, wireless base
station and other carrier-grade systems
G.8262/813 EEC/SEC, Telcordia Stratum 2-4
Copyright 2019. Microsemi Corporation. All Rights Reserved.
ZL30791, ZL30795, ZL30793
Product Brief
1. Block Diagram
PACKET_REF[2:0]
REF0P
REF0N
REF1P
REF1N
REF2P
REF2N
Register A ccess
One Diff / Two
Single-Ended
One Diff / Two
Single-Ended
One Diff / Two
Single-Ended
DPLL0
GP Synthesizer 0
general purpose
DIV
DIV
GPOUT0
GPOUT1
HPOUT0P
HPOUT0N
HPOUT1P
HPOUT1N
HPOUT2P
HPOUT2N
HPOUT3P
HPOUT3N
IntDiv
DIV
DIV
DPLL1
HP Synthesizer 1
low-jitte r
FracDiv
IntDiv
REF3P
REF3N
REF4P
REF4N
One Diff / Two
Single-Ended
One Diff / Two
Single-Ended
Reference Monitors
& State Machines
DIV
DIV
DPLL2
HP Synthesizer 2
low-jitte r
FracDiv
DIV
HPOUT4P
HPOUT4N
HPOUT5P
HPOUT5N
HPOUT6P
HPOUT6N
HPOUT7P
HPOUT7N
DIV
DIV
Microprocessor Port
SPI or I2C I/F & GPIO Pins
Master
Clock
XO
Optional x2
DIV
CS_B_ASEL0
SO_ASEL1
MCLKIN_N
MCLKIN_P
SRST_B
SCK_SCL
GPIO[8:0]
SI_SDA
RST_B
OSCI
OSCO
DPLL1 only present on ZL30795 and ZL30793
DPLL2 only present on ZL30793
Figure 1 - Functional Block Diagram
2. Application Example
TCXO
DPLL0
T4 path
BITS/SSU
GPS (1PPS)
Line
Extracted
Clocks[7:0]
Control info from
IEEE 1588 algorithm
Synth0
1.544 or 2.048MHz
CMOS to BITS/SSU
1 PPS or clock w/ embedded PPS
2x 156.25MHz
2x 125MHz
155.52MHz, 161.1328125MHz
or other frequency
to BITS/SSU system
DPLL1
SyncE
Synth1
SyncE signals to
system components
DPLL2
1588
Synth2
25MHz
1 PPS
1588 signals to
system components
Figure 2 - Synchronous Ethernet and IEEE 1588 Central Timing Application
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ZL30791, ZL30795, ZL30793
Product Brief
3. Detailed Features
3.1
Input Block Features
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Ten input reference pins; each can accept a CMOS signal or the POS side of a differential pair; or two
can be paired to accept both sides of a differential pair
Any input can be a SYNC signal for REF+SYNC frequency/phase/time locking
Any input can be a clock signal with embedded PPS signal (duty cycle distortion indicates PPS location)
Input clocks can be any frequency from 0.5Hz up to 900MHz (180MHz max for CMOS inputs)
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless
Inputs constantly monitored by programmable frequency and single-cycle monitors
Single-cycle monitor can quickly disqualify a reference when measured period is incorrect
Frequency measurement (ppb or Hz) and monitoring (coarse, fine, and frequency-step monitors)
Optional input clock invalidation on GPIO assertion to react to LOS signals from PHYs
Input-to-input phase measurement, 1ps resolution
Input-to-DPLL phase measurement, 1ps resolution
Per-input phase adjustment, 1ps resolution
One, two or three full-featured DPLLs
Very high-resolution DPLL architecture
State machine automatically transitions among freerun, tracking and holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 0.1mHz to 470Hz
Less than 0.1dB gain peaking
Fast frequency/phase/time lock capability for 1PPS or clock+1PPS input references
Programmable phase-slope limiting (PSL)
Programmable frequency rate-of-change limiting (FCL)
Programmable tracking range (i.e. hold-in range)
Truly hitless reference switching and mode switching
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Physical-to-physical reference switching
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Physical-to-packet reference switching
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Packet-to-physical reference switching
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Packet-to-packet reference switching
Per-DPLL phase adjustment, 1ps resolution
High-resolution frequency and phase measurement
Fast detection of input clock failure and transition to holdover mode
High-resolution holdover frequency averaging, better than 0.01ppb when using <10mHz filter
Time-of-Day registers: 48-bit seconds, 32-bit nanoseconds, writeable on input PPS edge
Any-to-any frequency conversion with 0ppm error
Two low-jitter synthesizers (Synth1, Synth2) with very high-resolution fractional scaling (i.e. non-integer
multiplication)
Two output dividers per low-jitter synthesizer: one integer (4 to 15 plus half divides 4.5 to 7.5) and one
40-bit fractional
One general-purpose synthesizer (Synth0)
A total of five output frequency families
Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter
components
Up to 16 single-ended outputs (up to 8 differential outputs) from Synth1 and Synth2
Each output can be one differential output or two CMOS outputs
Output clocks can be any frequency from 1Hz to 1045MHz (250MHz max for CMOS and HSTL outputs)
3.2
DPLL Features
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3.3
Synthesizer Features
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3.4
Low-Jitter Output Clock Features
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ZL30791, ZL30795, ZL30793
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Product Brief
Output jitter from Synth1 and Synth2 integer dividers is <0.3ps RMS
Output jitter from fractional dividers is <1ps RMS, many frequencies <0.5ps RMS
In CMOS mode, the HPOUTxN frequency can be an integer divisor of the HPOUTxP frequency
(Example 1: HPOUT3P 125MHz, HPOUT3N 25MHz. Example 2: HPOUT2P 25MHz, HPOUT2N 1Hz)
Outputs directly interface (DC coupled) with LVDS, LVPECL, HSTL, HCSL and CMOS components
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components
Can produce PCIe clocks
Sophisticated output-to-output phase alignment
Per-synthesizer phase adjustment, 1ps resolution
Per-output phase adjustment
Per-output duty cycle / pulse width configuration
Per-output enable/disable
Per-output glitchless start/stop (stop high or low)
Two CMOS outputs from Synth0
Any frequency from 0.5Hz to 180MHz
Output jitter is typically 20-30ps
Useful for applications where the component or system receiving the signal has low bandwidth such as
a central timing IC
Can output a clock signal with embedded PPS (ePPS) (duty cycle distortion indicates PPS location)
Operates from a single TCXO or OCXO. Acceptable frequencies: 23.75MHz to 25MHz, 47.5MHz to
50MHz, 114.285MHz to 125MHz. Best jitter:
48MHz.
Very-low-jitter applications can connect a TCXO or OCXO (any frequency, any output jitter) as the
stability reference and a low-cost low-jitter XO as the jitter reference
This ability to have separate jitter and stability references greatly reduces the cost of the TCXO or
OCXO (no jitter requirement, no high-frequency-requirement) and allows reuse of already-qualified
TCXO and OCXO components
Automatic self-configuration at power-up from internal Flash memory
Input-to-output alignment <200ps with external feedback
Fast REF+SYNC locking for frequency and 1PPS phase alignment with lower-cost oscillator
Generates output SYNC signals: 1PPS (IEEE 1588), 2kHz or 8kHz (SONET/SDH) or other frequency
JESD204B clocking: device clock and SYSREF signal generation with skew adjustment
Internal compensation for local oscillator frequency error in DPLLs and input monitors, 1ppt resolution
Numerically controlled oscillator (NCO) behavior allows system software to steer DPLL frequency or
fractional output divider frequency with resolution better than 0.005ppt
Spread-spectrum modulation available in each fractional output divider (PCIe compliant)
Seven general-purpose I/O pins each with many possible status and control options
SPI or I
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C serial microprocessor interface
3.5
General-Purpose Output Clock Features
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3.6
Local Oscillator
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3.7
General Features
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3.8
Evaluation Software
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Simple, intuitive Windows-based graphical user interface
Supports all device features and register fields
Makes lab evaluation of the device quick and easy
Generates configuration scripts to be stored in internal Flash memory
Generates full or partial configuration scripts to be run on a system processor
Works with or without an evaluation board
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ZL30791, ZL30795, ZL30793
Product Brief
4. Software Features
The following figure shows the Time Synchronization Algorithm system environment. The subsections below list the
features of the Time Synchronization Algorithm.
Host Processor
Application Layer
Control, Configuration, Stats & Alarms
Packet
Network
Microsemi
Ethernet
MAC & PHY
(Timestamp)
Microsemi
PLL
Transport
Layer
Protocols
Microsemi
ZLS30390
IEEE 1588-2008
Protocol Engine
Microsemi
ZLS30380
Time Sync
Algorithm
SyncE/
Stratum 3/
GNSS/
IEEE 1588
Clock
PPS
Operating System
Timestamp Reference Clock
4.1
Time Synchronization Algorithm
The Time Synchronization Algorithm is responsible to accurately synchronize the local clock to a selected Server.
The Time Synchronization Algorithm is synchronizing the Client to the Server to meet a variety of specifications or
applications related to frequency accuracy (FFO), frequency (MTIE, TDEV), phase (1 Hz or 1PPS) and time (UTC
& GNSS/GPS).
The Time Synchronization Algorithm can run on a variety of host processor architectures, whether embedded into
an SoC or on a dedicated small scale CPU (such as Microsemi’s SmartFusion2 SoC FPGA). The Time
Synchronization Algorithm will interconnect with a wide array of software-programmable clock generators (such as
Microsemi’s Network Synchronizer PLLs), protocol engines (such as Microsemi’s ZLS30390 IEEE 1588-2008
Protocol Engine) and underlying Ethernet MACs and PHYs that perform hardware timestamping.
4.2
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End Application Target Performance
Frequency offset accuracy performance for GSM, WCDMA-FDD, LTE-FDD femtocell, small cell
(residential, urban, rural, enterprise), picocell and macrocell applications, with target performance less than
± 15 ppb
Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT
EEC, PNT PEC and CES interface specifications
Phase Synchronization performance for WCDMA-TDD, Mobile WiMAX, TD-SCDMA, CDMA2000, LTE-
TDD, LTE-A, LTE-A Pro and 5G NR femtocell, small cell (residential, urban, rural, enterprise), picocell and
macrocell applications with target performance less than ± 1
s
phase alignment
Time Synchronization for TAI, UTC-traceability and GNSS/GPS replacement
The Time Synchronization Algorithm is suitable for many end application targets, including:
4.3
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Packet Networks
ITU-T G.8261 Appendix VI
ITU-T G.8261.1 network limit compliant
ITU-T G.8271.1 network limit compliant without SyncE
ITU-T G.8271.2 network limit compliant
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The Time Synchronization Algorithm is suitable for high performance over a variety of packet networks including:
Wireless Connectivity
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