EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

SQE48T30025-NDALG

Description
DC-DC Regulated Power Supply Module, 1 Output, Hybrid, ROHS COMPLIANT PACKAGE-8
CategoryPower/power management    The power supply circuit   
File Size532KB,29 Pages
ManufacturerBel Fuse
Environmental Compliance
Download Datasheet Parametric View All

SQE48T30025-NDALG Overview

DC-DC Regulated Power Supply Module, 1 Output, Hybrid, ROHS COMPLIANT PACKAGE-8

SQE48T30025-NDALG Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerBel Fuse
package instructionROHS COMPLIANT PACKAGE-8
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresREMOTE SHUTDOWN
Analog Integrated Circuits - Other TypesDC-DC REGULATED POWER SUPPLY MODULE
CertificationEN, IEC, UL
Efficiency (main output)89%
high10.34 mm
Maximum input voltage75 V
Minimum input voltage36 V
Nominal input voltage48 V
JESD-30 codeR-XDMA-P8
JESD-609 codee3
length58.42 mm
Number of functions1
Output times1
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output current30 A
Maximum output voltage2.75 V
Minimum output voltage2 V
Nominal output voltage2.5 V
Package body materialUNSPECIFIED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
surface mountNO
technologyHYBRID
Terminal surfaceMatte Tin (Sn) - with Nickel (Ni) barrier
Terminal formPIN/PEG
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Fine-tuning/adjustable outputYES
width22.76 mm
Base Number Matches1
[Rawpixel RVB2601 development board trial experience] 4. General hardware timer test
4. General Hardware Timer TestWhen using an operating system, if some tasks are performed in a software dead-wait manner, the system efficiency will inevitably be affected. Therefore, some slow period...
gs001588 XuanTie RISC-V Activity Zone
Ask a question about Verilog
I am a FPGA newbie, and now I have a Verilog question I would like to ask For example, there is an input data input [16:0] REG For ease of use, I now want to disassemble REG, such as a = REG[16:8]; b ...
littleshrimp FPGA/CPLD
Share MODBUS examples based on MSP430
This is the source code of the original author of tsg9456 in actual application, I hope it can help everyoneRun codeCopy code#include "synth.h"//-------------------------------------------------------...
火辣西米秀 Microcontroller MCU
Using FPGA to collect images and store them in SD card
I am currently working on using a camera to continuously capture several images in FPGA, storing the images in SDRAM, and want to store them in a SD card in bmp format. I don't know NIOS design, so I ...
微娴轩 EE_FPGA Learning Park
ATSAMD21, use ATMEL START to configure the internal DFLL48M CLOSE LOOP MODE to run at 48MHz
[b][color=#5E7384]This content is originally created by EEWORLD forum user [size=3]zhengwenbang[/size]. If you need to reprint or use it for commercial purposes, you must obtain the author's consent a...
zhengwenbang Microchip MCU
EEWORLD University ---- VLSI CADI - Theory
VLSI CADI-Theory : https://training.eeworld.com.cn/course/6101A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc.? How do we design these complex chips?? Answer: CAD s...
木犯001号 Embedded System

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号