QT92N5M-133.000MHZ datasheet, PDF

QT92N5M-133.000MHZ: DescriptionCRYSTAL OSCILLATOR, CLOCK, LVHCMOS OUTPUT; CategoryPassive components oscillator; File Size338KB，6 Pages; ManufacturerQ-TECH Corporation; Environmental Compliance

Download Datasheet Parametric View All

QT92N5M-133.000MHZ Overview

CRYSTAL OSCILLATOR, CLOCK, LVHCMOS OUTPUT

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Q-TECH Corporation
package instruction	ROHS COMPLIANT, HERMETIC SEALED, MINIATURE, CERAMIC, SMD, 4 PIN
Reach Compliance Code	compliant
Other features	ENABLE/DISABLE FUNCTION; TAPE AND REEL
maximum descent time	5 ns
Frequency Adjustment - Mechanical	NO
frequency stability	25%
JESD-609 code	e4
Manufacturer's serial number	QT92
Installation features	SURFACE MOUNT
Number of terminals	4
Maximum operating frequency	133 MHz
Minimum operating frequency	0.125 MHz
Nominal operating frequency	133 MHz
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Oscillator type	LVHCMOS
Output load	10 KOHM, 15 pF
Maximum output low current	4 mA
Package body material	CERAMIC
Encapsulate equivalent code	SMDIP4,.31,200
physical size	8.89mm x 7.37mm x 4.826mm
power supply	2.5 V
Certification status	Not Qualified
longest rise time	5 ns
Filter level	MIL-STD-883 Class B (Modified)
Maximum slew rate	35 mA
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	40/60 %
technology	CMOS
Terminal surface	Gold (Au) - with Nickel (Ni) barrier
Base Number Matches	1

[Rawpixel RVB2601 development board trial experience] 4. General hardware timer test: 4. General Hardware Timer TestWhen using an operating system, if some tasks are performed in a software dead-wait manner, the system efficiency will inevitably be affected. Therefore, some slow period...; gs001588 XuanTie RISC-V Activity Zone

Ask a question about Verilog: I am a FPGA newbie, and now I have a Verilog question I would like to ask For example, there is an input data input [16:0] REG For ease of use, I now want to disassemble REG, such as a = REG[16:8]; b ...; littleshrimp FPGA/CPLD

Share MODBUS examples based on MSP430: This is the source code of the original author of tsg9456 in actual application, I hope it can help everyoneRun codeCopy code#include "synth.h"//-------------------------------------------------------...; 火辣西米秀 Microcontroller MCU

Using FPGA to collect images and store them in SD card: I am currently working on using a camera to continuously capture several images in FPGA, storing the images in SDRAM, and want to store them in a SD card in bmp format. I don't know NIOS design, so I ...; 微娴轩 EE_FPGA Learning Park

ATSAMD21, use ATMEL START to configure the internal DFLL48M CLOSE LOOP MODE to run at 48MHz: [b][color=#5E7384]This content is originally created by EEWORLD forum user [size=3]zhengwenbang[/size]. If you need to reprint or use it for commercial purposes, you must obtain the author's consent a...; zhengwenbang Microchip MCU

EEWORLD University ---- VLSI CADI - Theory: VLSI CADI-Theory : https://training.eeworld.com.cn/course/6101A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc.? How do we design these complex chips?? Answer: CAD s...; 木犯001号 Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components