M54/74HC292/7292
M54/74HC294/7294
PROGRAMMABLE DIVIDER/TIMER
.
.
.
.
.
.
.
.
HIGH SPEED
f
MAX
= 70 MHz (TYP.) at V
CC
= 5 V
LOW POWER DISSIPATION
o
I
CC
= 4 mA (MAX.) at T
A
= 25 C
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
| I
OH
|= I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE WITH
54/74LS292/294
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R
M74HCXXXM1R
M74HCXXXB1R
M74HCXXXC1R
DESCRIPTION
The 54/74HC292/7292 and HC294/7294 are high
speed CMOS PROGRAMMABLE DIVIDER/TIMER
fabricated with silicon C
2
MOS technology.
They achieve the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low
power dissipation.
These devices are programmable frequency
dividers. The types have two clock inputs, either one
may be used for clock gating. (see the function
table). The HC292/7292 can divide from 2
2
to 2
31
,
and the HC294/7294 can divide from 2
2
to 2
15
. The
PIN CONNECTION
(top view)
HC292
HC7292
HC294
HC7294
HC292
HC7292
HC294
HC7294
types feature an active-low clear input to initialize
the state of all flip-flops. To facilitate incoming
inspection, test points are provided. (TP1, TP2 and
TP3 on the HC292/7292 and TP on the
HC294/7294). All inputs are equipped with
protection circuits against static discharge and
transient excess voltage.
HC292/294 have Q output with ”Totem pole”
configuration and test point TP with ”Open Drain”
output configuration.
HC7292/7294 have all outputs ”Totem Pole”.
October 1993
1/14
M54/M74HC292/7292/294/7294
INPUT AND OUTPUT EQUIVALENT CIRCUIT
(TOTEM POLE OUTPUT)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
(OPEN DRAIN OUTPUT, HC292/294)
PIN DESCRIPTION
(HC292/7292)
PIN No
4, 5
1, 2, 10,
14, 15
3, 6, 13
11
7
8
16
SYMBOL
CLK1,
CLK2
A to E
TP1, TP2,
TP3
CLR
Q
GND
V
CC
NAME AND FUNCTION
input Clock
Program Inputs
Test Point Outputs
Clear (Active LOW)
Output
Ground (0V)
Positive Supply Voltage
PIN DESCRIPTION
(HC294/7294)
PIN No
4, 5
1, 2, 14, 15
3
11
7
8
16
SYMBOL
CLK1,
CLK2
A to D
TP1
CLR
Q
GND
V
CC
NAME AND FUNCTION
input Clock
Program Inputs
Test Point Output
Clear (Active LOW)
Output
Ground (0V)
Positive Supply Voltage
IEC LOGIC SYMBOLS
HC292/HC7292
HC294/HC7294
TRUTH TABLE
CLEAR
L
H
H
H
H
CLOCK1
X
L
H
X
CLOCK2
X
L
X
H
Q OUTPUT MODE
CLEARED TO L
UP COUNT
NO CHANGE
2/14
FPGA/CPLD
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