3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
3.3V PROGRAMMABLE
SKEW DUAL PLL CLOCK
DRIVER TURBOCLOCK™ W
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ref input is 5V tolerant
8 pairs of programmable skew outputs
Two separate A and B banks for individual control
Low skew: 185ps same pair, 250ps same bank, 350ps both
banks
Selectable positive or negative edge synchronization on each
bank: excellent for DSP applications
Synchronous output enable on each bank
Input frequency: 2MHz to 200MHz
Output frequency: 6MHz to 200MHz
3-level inputs for skew and PLL range control
3-level inputs for feedback divide selection multiply / divide
ratios of (1-6, 8, 10, 12) / (2, 4)
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Power-down mode on each bank
Lock indicator on each bank
Available in BGA package
IDT5V9955
DESCRIPTION
The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V9955 has sixteen programmable skew
outputs in eight banks of 2. The two separate PLLs allow the user to
independently control A and B banks. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.
The feedback input allows divide-by-functionality from 1 to 12 through
the use of the xDS[1:0] inputs. This provides the user with frequency
multiplication from 1 to 12 without using divided outputs for feedback.
When the xsOE pin is held low, all the xbank outputs are synchronously
enabled. However, if xsOE is held high, all the xbank outputs except x2Q0
and x2Q1 are synchronously disabled. The xLOCK is high when the
xbank PLL has achieved phase lock.
Furthermore, when xPE is held high, all the outputs are synchronized
with the positive edge of the REF clock input. When xPE is held low, all the
xbank outputs are synchronized with the negative edge of REF. The
IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
A
LOCK
A
FS
A
PE
REF
APD
A
sOE
TEST
B
PE
B
FS
B
LOCK
BPD
BsOE
3
3
PLL
/N
3
3
ADS1:0
A1Q
0
A1Q
1
Skew
Select
3
A1F1:0
3
B1F1:0
3
BDS1:0
3
Skew
Select
A
FB
B
FB
3
/N
3
3
PLL
3
B1Q
0
B1Q
1
A2Q
0
A2Q
1
Skew
Select
3
A2F1:0
3
B2F1:0
3
3
Skew
Select
B2Q
0
B2Q
1
A3Q
0
A3Q
1
3
Skew
Select
A3F1:0
3
B3F1:0
3
3
Skew
Select
B3Q
0
B3Q
1
A4Q
0
A4Q
1
Skew
Select
3
A4F1:0
3
B4F1:0
3
3
Skew
Select
B4Q
0
B4Q
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2004
Integrated Device Technology, Inc.
NOVEMBER 2004
DSC 5974/11
IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
A3Q
1
A4Q
0
A4Q
1
A
PE
A
PD
A4F
1
A3F
1
AFS
B2F
1
B1F
1
BDS
1
B
LOCK
BV
DDQ
B1Q
0
B1Q
1
BGND
BGND
BGND
BGND
B4Q
0
R
B2Q
0
B2Q
1
BFB
BGND
B3Q
0
B3Q
1
T
5
A3Q
0
AGND
AFB
A2Q
1
A2Q
0
A
AGND
AGND
AGND
AGND
A1Q
1
B
AGND
AGND
AGND
AGND
A1Q
0
C
AGND
AV
DDQ
AV
DDQ
AV
DDQ
AV
DDQ
D
A
S
OE
AV
DDQ
AV
DDQ
ADS0
A
LOCK
E
A4F
0
AV
DDQ
AV
DDQ
A1F
0
ADS
1
F
A3F
0
AV
DDQ
AV
DDQ
A2F
0
A1F
1
G
AV
DD
AV
DDQ
REF
AGND
A2F
1
H
BGND
TEST
BV
DDQ
BV
DD
BFS
J
B2F
0
BV
DDQ
BV
DDQ
B3F
0
B3F
1
K
B1F
0
BV
DDQ
BV
DDQ
B4F
0
B4F
1
L
BDS
0
BV
DDQ
BV
DDQ
B
S
OE
B
PD
M
BV
DDQ
BV
DDQ
BV
DDQ
BGND
B
PE
N
BGND
BGND
BGND
BGND
B4Q
1
P
4
3
2
1
FPBGA
TOP VIEW
96 BALL FPBGA PACKAGE ATTRIBUTES
1.5mm Max.
1.4mm Nom.
1.3mm Min.
0.8mm
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TOP VIEW
A
1
2
3
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
5.5mm
4
5
6
13.5mm
2
IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDQ
, V
DD
V
I
Description
Supply Voltage to Ground
DC Input Voltage
REF Input Voltage
Maximum Power
Dissipation
T
STG
T
A
= 85°C
T
A
= 55°C
Max
–0.5 to +4.6
–0.5 to V
DD
+0.5
–0.5 to +5.5
1.1
1.9
–65 to +150
°C
Unit
V
V
V
W
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
Description
Input Capacitance
REF
Others
Typ.
8
5
Max.
10
7
Unit
pF
NOTE:
1. Capacitance applies to all inputs except TEST, xFS, xnF
[1:0]
, and xDS
[1:0]
.
Storage Temperature Range
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
PIN DESCRIPTION
Pin Name
REF
xFB
TEST
(1)
xsOE
(1)
Type
IN
IN
IN
IN
Description
Reference Clock Input
Individual Feedback Inputs for A and B banks
When MID or HIGH, disables PLL for A and B banks (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See
Control Summary Table) remain in effect. Set LOW for normal operation.
Individual Synchronous Output Enable for A and B banks. When HIGH, it stops clock outputs (except x2Q
0
and x2Q
1
) in a LOW state
(for xPE = H) - x2Q
0
and x2Q
1
may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and
sOE
is HIGH, the nF[
1:0
] pins act as output disable controls for individual banks when xnF[
1:0
] = LL. Set xsOE LOW for normal operation
(has internal pull-down).
Individual Selectable positive or negative edge control for A and B banks. When LOW/HIGH the outputs are synchronized with the negative/
positive edge of the reference clock (has internal pull-up).
xnF
[1:0]
xFS
xnQ
[1:0]
xDS
[1:0]
xPD
xLOCK
V
DDQ
V
DD
GND
IN
IN
OUT
IN
IN
OUT
PWR
PWR
PWR
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Individual control on A
and B banks.
Eight banks of two outputs with programmable skew
3-level inputs for feedback divider selection for A and B banks
Power down control. Shuts off either A or B bank of the chip when LOW (has internal pull-up).
PLL lock indication signal for A and B banks. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be
synchronized to the inputs. (For more information on application specific use of the LOCK pin, please see AN237.)
Power supply for output buffers
Power supply for phase locked loop, lock output, and other internal circuitry
Ground
xPE
IN
NOTE:
1. When TEST = MID and xsOE = HIGH, PLL remains active with xnF[
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless xnF[
1:0
] = LL.
3
IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (t
U
) which ranges
from 625ps to 1.3ns (see Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the xnF
1:0
control pins. In
order to minimize the number of control pins, 3-level inputs (HIGH-MID-
LOW) are used, they are intended for but not restricted to hard-wiring.
Undriven 3-level inputs default to the MID level. Where programmable
skew is not a requirement, the control pins can be left open for the zero
skew default setting. The Control Summary Table shows how to select
specific skew taps by using the xnF
1:0
control pins.
EXTERNAL FEEDBACK
By providing two separate external feedbacks, the IDT5V9955 gives
users flexibility with regard to skew adjustment. The xFB signal is com-
pared with the input REF signal at the phase detector in order to drive
the VCO. Phase differences cause the VCO of the PLL to adjust up-
wards or downwards accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
xFS = LOW
Timing Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1,2)
Skew Adjustment Range
(3)
Max Adjustment:
±7.8125ns
±67.5°
±18.75%
Example 1, F
NOM
= 25MHz
Example 2, F
NOM
= 37.5MHz
Example 3, F
NOM
= 50MHz
Example 4, F
NOM
= 75MHz
Example 5, F
NOM
= 100MHz
Example 6, F
NOM
= 150MHz
Example 7, F
NOM
= 200MHz
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
—
—
—
—
±7.8125ns
±135°
±37.5%
—
—
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
—
—
±7.8125ns
±270°
±75%
—
—
—
—
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
ns
Phase Degrees
% of Cycle Time
1/(32 x F
NOM
)
24 to 50MHz
xFS = MID
1/(16 x F
NOM
)
48 to 100MHz
xFS = HIGH
1/(8 x F
NOM
)
96 to 200MHz
Comments
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on xFS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at x1Q
1:0
, x2Q
1:0
, and
the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and xFB inputs will be F
NOM
when the output connected to xFB is
undivided and xDS[
1:0
] = MM. The frequency of the REF and xFB inputs will be F
NOM
/2 or F
NOM
/4 when the part is configured for frequency multiplication by using a divided
output as the xFB input and setting xDS[
1:0
] = MM. Using the xDS[
1:0
] inputs allows a different method for frequency multiplication (see Divide Selection Table).
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed xQ output is used for feedback, then adjustment range will be greater. For example
if a 4t
U
skewed output is used for feedback, all other outputs will be skewed –4t
U
in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6t
U
skew adjustment is possible and at the lowest F
NOM
value.
4
IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
DIVIDE SELECTION TABLE
xDS [
1:0
]
LL
LM
LH
ML
MM
MH
HL
HM
HH
xFB Divide-by-n
2
3
4
5
1
6
8
10
12
Permitted Output Divide-by-n connected to xFB
(1)
1 or 2
1
1, 2, or 4
1 or 2
1, 2, or 4
1 or 2
1 or 2
1
1
NOTE:
1. Permissible output division ratios connected to xFB. The frequency of the REF input will be F
NOM
/N when the part is configured for frequency multiplication by using an undivided
output for xFB and setting xDS[
1:0
] to N (N = 1-6, 8, 10, 12).
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
LL
(1)
LM
LH
ML
MM
MH
HL
HM
HH
Skew (Pair #1, #2)
–4t
U
–3t
U
–2t
U
–1t
U
Zero Skew
1t
U
2t
U
3t
U
4t
U
Skew (Pair #3)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Divide by 4
Skew (Pair #4)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Inverted
(2)
NOTES:
1. LL disables outputs if TEST = MID and xsOE = HIGH.
2. When pair #4 is set to HH (inverted), xsOE disables pair #4 HIGH when xPE = HIGH, xsOE disables pair #4 LOW when xPE = LOW.
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