EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

M5LV-320/256-15VC

Description
EE PLD, 7.5 ns, PQFP100
Categorysemiconductor    Programmable logic devices   
File Size536KB,47 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric View All

M5LV-320/256-15VC Overview

EE PLD, 7.5 ns, PQFP100

M5LV-320/256-15VC Parametric

Parameter NameAttribute value
Number of input and output buses74
Number of terminals100
Minimum operating temperature0.0 Cel
Maximum operating temperature70 Cel
stateTransferred
Programmable logic typeEE PLD
clock_frequency_max71.4 MHz
in_system_programmableYES
jesd_30_codeS-PQFP-G100
jtag_bsYES
Dedicated input quantity0.0
umber_of_macro_cells128
organize0 DEDICATED INPUTS, 74 I/O
Output functionMACROCELL
Packaging MaterialsPLASTIC/EPOXY
ckage_codeQFP
ckage_equivalence_codeQFP100,.63SQ,20
packaging shapeSQUARE
Package SizeFLATPACK
wer_supplies3.3
gation_delay7.5 ns
qualification_statusCOMMERCIAL
sub_categoryProgrammable Logic Devices
Rated supply voltage3.3 V
Minimum supply voltage3 V
Maximum supply voltage3.6 V
surface mountYES
CraftsmanshipCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal spacing0.5000 mm
Terminal locationQUAD
dditional_feature128 MACROCELLS
[ESP32-S2-Kaluga-1 Review] 5. Use LGVL to create a low-level interface?
I updated the IDF and found that the USB interface has changed a lot. Fortunately, I managed to get it connected in time. I don’t know why, but I just use it....
RCSN Domestic Chip Exchange
Kill TPS54340
The price of TPS54340 has risen from 3.5 to 15 yuan. Now 431 is used as the reference and loop, 5 BJTs are used for PWM+DRV, and NMOS is promoted. The replacement cost is 1.2 yuan. The efficiency is e...
PowerAnts Power technology
I have a hard time without a college diploma.
It's hard to get a job interview with a high school diploma without a college diploma....
懒人一个1 TI Technology Forum
Why is the voltage ringing spike of MOSFET different in boost and buck mode?
For bidirectional DC converters, some tubes have large voltage ringing spikes when boosting, but the voltage is much improved when stepping down, and the opposite is true for some tubes. In addition t...
squareshawn PCB Design
The circuit for discharging the PFC output capacitor is shown in Figure 2.
I would like to ask how to calculate the resistance value and choose the model of the resistor? I only know that this should use the RC discharge curve to calculate the resistance value and power? I d...
西里古1992 Analog electronics
Basic syntax of Verilog HDL
Verilog HDL is a language used for digital logic circuit design. The circuit design described by Verilog HDL is the Verilog HDL model of the circuit. Verilog HDL is both a behavioral description langu...
小柳叶 FPGA/CPLD

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号