'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-I,-85VLL-I,
-70VXL-I,-85VXL-I
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5256DFP,VP,RV is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is fabricated using
high-performance 3 polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough for battery back-up application. It is ideal for the memory
systems which require simple interface.
Especially the M5M5256DVP,RV are packaged in a 28-pin thin
small outline package.Two types of devices are available,
M5M5256DVP(normal lead bend type package),
M5M5256DRV(reverse lead bend type package). Using both types of
devices, it becomes very easy to design a printed circuit board.
PIN CONFIGURATION (TOP VIEW)
A14
A12
1
2
A7
3
A6
4
A5
5
A4
6
7
A3
A2
8
A1
9
A0
10
DQ1 11
DQ2 12
DQ3 13
GND 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/W
A13
A8
A9
A11
/OE
A10
/S
DQ8
DQ7
DQ6
DQ5
DQ4
M5M5256DFP
-I
FEATURE
Type
Access Power supply current
time
Active Stand-by
(max)
(max)
(max)
70ns
24µA
M5M5256DFP,VP,RV-85VLL
85ns
25mA
(Vcc=3.6V)
(Vcc=3.6V)
Outline 28P2W-C (DFP)
22 /OE
23 A11
24 A9
25 A8
26 A13
27 /W
28Vcc
1 A14
2 A12
3 A7
4 A6
5 A5
6 A4
7 A3
A10 21
/S 20
DQ8 19
DQ7 18
DQ6 17
DQ5 16
DQ415
GND 14
DQ3 13
DQ2 12
DQ1 11
A0 10
A1 9
A2 8
M5M5256DFP,VP,RV-70VLL
M5M5256DFP,VP,RV-70VXL
M5M5256DFP,VP,RV-85VXL
70ns
85ns
4.8µA
(Vcc=3.6V)
0.05µA
(Vcc=3.0V,
Typical)
M5M5256DVP
-I
•Single +3.3±0.3V power supply
•No clocks, no refresh
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prevents data contention in the I/O bus
•Common Data I/O
•Battery backup capability
•Low stand-by current··········0.05µA(typ.)
Outline 28P2C-A (DVP)
PACKAGE
M5M5256DFP
: 28 pin 450 mil SOP
M5M5256DVP,RV : 28pin 8 X 13.4 mm
2
TSOP
APPLICATION
Small capacity memory units
7 A3
6 A4
5 A5
4 A6
3 A7
2 A12
1 A14
28 Vcc
27 /W
26 A13
25 A8
24 A9
23 A11
22 /OE
M5M5256DRV
-I
A2 8
A1 9
A0 10
DQ1 11
DQ2 12
DQ3 13
GND 14
DQ4 15
DQ5 16
DQ6 17
DQ7 18
DQ8 19
/S 20
A10 21
Outline 28P2C-B (DRV)
MITSUBISHI
ELECTRIC
1
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-I,-85VLL-I,
-70VXL-I,-85VXL-I
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5256DP,KP,FP,VP,RV is
determined by a combination of the device control inputs /S,
/W and /OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
/W, /S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable /OE directly controls the output stage. Setting the
/OE at a high level,the output stage is in a high-impedance
state, and the data bus contention problem in the write cycle
is eliminated.
A read cycle is executed by setting /W at a high level and
/OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
FUNCTION TABLE
/S
H
L
L
L
/W
X
L
H
H
/OE
X
X
L
H
Mode
Non selection
Write
Read
DQ
High-impedance
D
IN
D
OUT
High-impedance
Icc
Stand-by
Active
Active
Active
BLOCK DIAGRAM
A8
A 13
A 14
A 12
A7
A6
A5
A4
ADDRESS
INPUT
A3
25
26
ADDRESS INPUT
BUFFER
ROW DECODER
1
2
2
3
4
5
6
7
32768 WORD
SENSE ANPLIFIER
OUTPUT BUFFER
X 8BIT
11
12
13
15
16
17
18
19
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DATA I/O
(512 ROWS X
512 COLUMNS)
A2
A1
A0
A 10
A 11
A9
WRITE CONTROL
INPUT /W
CHIP SELECT
INPUT
/S
8
DATA INPUT
BUFFER
COLUMN
DECODER
9
10
21
23
24
ADDRESS INPUT
BUFFER
CLOCK
GENERATOR
27
20
28
14
VCC
(3.3V)
GND
(0V)
OUTPUT ENABLE
/OE
INPUT
22
MITSUBISHI
ELECTRIC
2
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-I,-85VLL-I,
-70VXL-I,-85VXL-I
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply voltage
Vcc
V
I
V
O
P
d
T
opr
T
stg
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to GND
Ta=25°C
Ratings
-0.3
*
~4.6
-0.3
*
~Vcc+0.3
(Max 4.6)
Unit
V
V
V
mW
°C
°C
0~Vcc
700
-40~85
-65~150
* -3.0V in case of AC ( Pulse width
≤
30ns )
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage 1 I
OH
=-0.5mA
(Ta=-40~85°C, Vcc=3.3±0.3V, unless otherwise noted)
Test conditions
Limits
Min
2.0
-0.3
*
2.4
Vcc
-0.5
Typ
Max
Vcc
+0.3
Unit
V
V
V
V
0.6
High-level output voltage 2 I
OH
=-0.05mA
Low-level output voltage
Input current
Output current in off-state
Active supply current
(AC, MOS level )
I
OL
=1mA
V
I
=0
~
Vcc
/S=V
IH
or or /OE=V
IH
,
V
I/O
=0
~
Vcc
Min.
/S≤0.2V,
cycle
Other inputs<0.2V or >Vcc-0.2V
1MHz
Output-open Min. cycle
/S=V
IL
,
other inputs=V
IH
or V
IL
Output-open Min. cycle
/S≥Vcc-0.2V,
other inputs=0~Vcc
/S=V
IH
,other inputs=0
~
Vcc
Min.
cycle
1MHz
-VLL
-VXL
0.05
13
1.5
14
1.5
0.4
±1
±1
25
V
uA
uA
Icc
1
mA
3
25
mA
3
24
4.8
0.33
uA
mA
Icc
2
Active supply current
(AC, TTL level )
Icc
3
Icc
4
Stand-by current
Stand-by current
* -3.0V in case of AC ( Pulse width
≤
30ns )
CAPACITANCE
Symbol
C
I
C
O
(Ta=-40~85°C, Vcc=3.3±0.3V, unless otherwise noted)
Parameter
Input capacitance
Output capacitance
Test conditions
V
I
=GND, V
I
=25mVrms, f=1MHz
V
O
=GND,V
O
=25mVrms, f=1MHz
Min
Limits
Typ Max
6
8
Unit
pF
pF
Note 0: Direction for current flowing into an IC is positive (no mark).
1: Typical value is one at Ta = 25°C.
2: C
I
, C
O
are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
3
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-I,-85VLL-I,
-70VXL-I,-85VXL-I
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) MEASUREMENT CONDITIONS
(Ta = -40~85°C, Vcc=3.3±0.3V, unless otherwise noted )
Input pulse level···················V
IH
=2.2V,V
IL
=0.4V
Input rise and fall time··········5ns
Reference level····················V
OH
=V
OL
=1.5V
Output loads·························Fig.1,CL=30pF (-70VLL,-70VXL )
CL=50pF (-85VLL,-85VXL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
1TTL
DQ
(Including
scope and JIG)
C
L
Fig.1 Output load
(2) READ CYCLE
Symbol
t
CR
t
a
(A)
t
a
(S)
t
a
(OE)
t
dis
(S)
t
dis
(OE)
t
en
(S)
t
en
(OE)
t
V
(A)
Parameter
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after /S high
Output disable time after /OE high
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
Limits
-70VLL, VXL -85VLL, VXL
Min Max Min Max
70
85
70
85
70
85
35
45
25
25
25
25
5
10
5
10
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Limits
-70VLL, VXL -85VLL, VXL Unit
Symbol
Parameter
Min Max Min Max
ns
t
CW
70
85
Write cycle time
t
w
(W)
ns
Write pulse width
55
60
t
su
(A)
ns
Address setup time
0
0
t
su
(A-WH)
Address setup time with respect to /W high 65
ns
70
t
su
(S)
ns
Chip select setup time
65
70
t
su
(D)
ns
Data setup time
30
35
t
h
(D)
ns
Data hold time
0
0
t
rec
(W)
ns
Write recovery time
0
0
t
dis
(W)
ns
Output disable time from /W low
25
25
t
dis
(OE)
Output disable time from /OE high
ns
25
25
t
en
(W)
ns
Output enable time from /W high
5
10
t
en
(OE)
ns
Output enable time from /OE low
5
10
MITSUBISHI
ELECTRIC
4
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL-I,-85VLL-I,
-70VXL-I,-85VXL-I
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
A
0~14
t
a
(A)
t
a
(S)
/S
(Note 3)
t
CR
t
v
(A)
t
a
(OE)
t
en
(OE)
t
dis
(S)
(Note 3)
/OE
(Note 3)
t
dis
(OE)
t
en
(S)
(Note 3)
DQ
1~8
/W = "H" level
DATA VALID
Write cycle (/W control mode)
A
0~14
t
CW
t
su
(S)
/S
(Note 3)
(Note 3)
t
su
(A-WH)
/OE
t
su
(A)
/W
t
dis
(W)
t
dis
(OE)
DQ
1~8
(Note 3)
t
w
(W)
t
rec
(W)
t
en
(W)
t
en
(OE)
DATA IN
STABLE
(Note 3)
t
su
(D)
t
h
(D)
MITSUBISHI
ELECTRIC
5
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