ISO 9001 CERTIFIED BY DSCC
M.S.KENNEDY CORP.
10 AMP, 75V, 3 PHASE MOSFET
BRIDGE WITH INTELLIGENT
INTEGRATED GATE DRIVE
4300
(315) 701-6751
4707 Dey Road Liverpool, N.Y. 13088
FEATURES:
75 Volt Motor Supply Voltage
10 Amp Output Switch Capability, All N-Channel MOSFET Output Bridge
100% Duty Cycle High Side Conduction Capable
Suitable for PWM Applications from DC to 100KHz
Shoot-Through/Cross Conduction Protection
Undervoltage Lockout Protection
Programmable Dead-Time Control
Low Active Enable for Bridge Shutdown Control
Isolated Package Design for High Voltage Isolation Plus Good Thermal Transfer
Available with Three Lead Bend Options
MIL-PRF-38534 QUALIFIED
DESCRIPTION:
The MSK 4300 is a 3 phase MOSFET bridge plus drivers in a convenient isolated hermetic package. The hybrid is
capable of 10 amps of output current and 75 volts of DC bus voltage. It has a full line of protection features,
including undervoltage lockout protection of the bias voltage, cross conduction control and a user programmable
dead-time control for shoot-through elimination. In addition, the bridge may be shut down by using the EN (enable)
control. The MSK 4300 provides good thermal conductivity for the MOSFETs due to the electrically isolated package
design that allows direct heat sinking of the device without insulators.
EQUIVALENT SCHEMATIC
TYPICAL APPLICATIONS
3 Phase Brushless DC
Servo Control
Fin Actuator Control
Gimbal Control
3 Phase AC
Induction Motor Control
HVAC Blower Control
1
Rev. C 6/00
ABSOLUTE MAXIMUM RATINGS
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-55°C to +125°C
+150°C
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ELECTRICAL SPECIFICATIONS
Parameter
CONTROL SECTION
V
BIAS
Quiescent Current
V
BIAS
Operating Current
Undervoltage Threshold (Falling)
Undervoltage Threshold (Rising)
Low Level Input Voltage
High Level Input Voltage
Low Level Input Current
High Level Input Current
OUTPUT BRIDGE
Drain-Source Breakdown Voltage
Drain-Source Leakage Current
Drain-Source On Resistance
SWITCHING CHARACTERISTICS
Rise Time
Fall Time
1
1
V+=30V, R
L
=3Ω
I
D
=10A
SWR Resistor=
∞
SWR Resistor=
∞
SWR Resistor=
∞
SWR Resistor=
∞
SWR =
∞
SWR=12K
1
1
I
SD
=10A
I
SD
=10A, di/dt=100A/µS
-
-
4
4
4
4
4
4
-
-
-
-
-
-
-
-
6.0
0.3
-
-
5
6
0.5
5
5
0.5
7.0
0.5
1.05
75
-
-
2
8
8
2
8.0
0.7
1.25
-
-
-
-
-
-
-
6.0
0.3
-
-
5
6
0.5
5
5
0.5
7.0
0.5
1.05
75
-
-
3
10
10
3
8.0
0.7
1.25
-
nSec
nSec
µSec
µSec
µSec
µSec
µSec
µSec
Volts
nSec
1
1
1
I
D
=25µA, All Inputs Off
V
DS
=70V
I
D
=10A
-
-
1
-
70
-
-
-
-
-
-
-
-
25
0.300
0.16
70
-
-
-
-
-
-
-
-
25
0.300
0.16
V
µAmp
Ω
Ω
1
1
1
1
V
IN
=0V
V
IN
=5V
All Inputs Off
f=20KHz, 50% Duty Cycle
1,2,3
1,2,3
1
1
-
-
-
-
5.75
6.2
-
2.7
60
-1
2.5
12.5
6.6
7.1
-
-
100
-
8
15
7.5
8.0
0.8
-
135
+1
5.75
6.2
-
2.7
60
-1
2.5
12.5
6.6
7.1
-
-
100
-
8
15
7.5
8.0
0.8
-
135
+1
mAmp
mAmp
Volts
Volts
Volts
Volts
µAmp
µAmp
Test Conditions
GroupA
4
Subgroup
Min.
MSK 4300H
3
Typ.
Max.
Min.
MSK 4300
2
Typ.
Max.
Units
Drain-Source On Resistance (Each FET)
(Each FET, For Thermal Calculations Only)
Turn-On Prop Delay (Lower)
Turn-Off Prop Delay (Lower)
Turn-On Prop Delay (Upper)
Turn-Off Prop Delay (Upper)
Dead Time
Dead Time
SOURCE-DRAIN DIODE CHARACTERISTICS
Forward Voltage
Reverse Recovery Time
NOTES:
1
2
3
4
5
Guaranteed by design but not tested. Typical parameters are representative of actual device
performance but are for reference only.
Industrial grade devices shall be tested to subgroups 1 and 4 unless otherwise specified.
Military grade devices ("H" Suffix) shall be 100% tested to Subgroups 1, 2, 3 and 4.
Subgroups 5 and 6 testing available upon request.
Subgroup 1, 4 T
A
= T
C
= +25°C
2, 5 T
A
= T
C
= +125°C
3, 6 T
A
= T
C
= -55°C
2
Rev. C 6/00
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V+
V
BIAS
V
IND
I
OUT
I
PK
High Voltage Supply
75V
Bias Supply
16V
Logic Input Voltages
-0.3V to V
BIAS
+0.3V
Continuous Output Current
10A
Peak Output Current
25A
θ
JC
Thermal Resistance
T
ST
Storage Temperature Range
T
LD
Lead Temperature Range
(10 Seconds)
T
C
Case Operating Temperature
T
J
Junction Temperature
9°C/W
-65°C to +150°C
+300°C
APPLICATION NOTES
MSK 4300 PIN DESCRIPTIONS
AL,BL,CL
- Are the lowside logic level digital inputs. These
three inputs control the three lowside bridge transistors. If the
highside inputs are low, then the lowside inputs will control
both the lowside and the highside of the bridge, with deadtime
set by the SWR resistor. EN will override these inputs, forcing
all outputs low. These inputs can be driven by logic up to 15V
(less than VBIAS). An internal pullup to VBIAS will hold each
input high if the pins are not driven.
AH,BH,CH
- Are the highside logic level digital inputs. These
three inputs control the three highside bridge transistors. Un-
less the deadtime is disabled by connecting SWR to ground,
the lowside input of each phase will override the corresponding
highside input. If SWR is the lowside input of each phase will
override the corresponding highside input. In this condition,
tied to ground, deadtime is disabled and the outputs follow the
inputs. In this condition, shoot-through must be avoided exter-
nally. EN will override all inputs, forcing outputs low.
VBIAS
- Is the positive supply for the gate drive. This pin should
be decoupled to ground with at least a 10µF capacitor.
GROUND
- Is the return for the VBIAS supply. This pin should
be connected to the return of the lowside MOSFETs or the
bottom of the sense resistor at the bottom of the bridge. The
gate drive current must return through this pin, so trace lengths
should be kept to a minimum. All grounds should be returned
to the bottom of the bridge or sense resistor in a star fashion.
This will eliminate ground loops.
SWR
- Is the pin for controlling the deadtime between the top
and bottom transistors of the bridge. By connecting a pullup
resistor between this pin and VBIAS, various deadtimes can be
obtained. There is and internal 100KΩ pullup resistor connected
internally. By adding additional resistors in parallel externally,
reduced deadtimes can be achieved. By connecting this pin to
ground, all deadtime is eliminated. However, care must be taken
to assure that deadtime is being generated by the logic circuitry
driving the inputs. Shoot-through can occur (both the top and
bottom transistors on at the same time for a given phase, caus-
ing a short on the V+ supply to ground) destroying the bridge.
V+
- Is the power connection for the top of the output bridge.
This pin must be bypassed by a capacitor to ground of a least
10µF per amp of output current minimum, and high quality high
frequency bypass capacitance to help suppress switching noise.
AØ, BØ, CØ
- Are the output pins for the three phases of the
power bridge.
EN
- Is the enabling input for the bridge. This digital input,
when pulled low, will enable the bridge, following the inputs
from AL, BL, CL and AH, BH, CH inputs. When pulled high, it
will override all other inputs and disable the bridge. It is inter-
nally pulled high to VBIAS, and can be driven by logic levels up
to VBIAS.
RSENSE
- Are the connections to the bottom of the bridge. All
power flowing through the bridge will flow through this point,
and can be sensed by connecting a sense resistor from here to
ground. The sense resistor will develop a voltage proportional
to the current flowing. Size the value and power rating of the
sense resistor according to the voltage necessary. 3 volts is
the maximum voltage between this point and ground, or dam-
age to the hybrid will result.
3
BUS VOLTAGE FILTER CAPACITORS
The size and placement of the capacitors for the main voltage
bus for the motor will have an effect on the noise filtered through-
out the rest of the system. Series RLC tuned circuit is being
created by the inductance of the wire (about 30nH per inch),
the filter capacitance, and all of the resistances (wire resistance
and the capacitor ESR) of the overall power circuit. Voltage
spikes from the back EMF if the motor ride on top of the bus
voltage. All of this must be taken into account when laying out
the system. A first capacitor of high quality and low ESR should
be placed as close to the hybrid circuit as possible. Along with
that, a capacitor of 5x to 10x the first value should be added
(and that second capacitor should have some ESR) and/or a
resistor should be added to help with the damping of the volt-
age spikes. Be careful of the ripple current in all the capacitors.
Excessive ripple current, beyond what the capacitor is rated
for, will destroy the capacitor.
BIAS SUPPLY BYPASS CAPACITORS
It is recommended that at least 10µF of capacitance for by-
passing the VBIAS voltage that supplies the drive circuitry for
the MSK 4300, along with 0.1µF for helping the high frequency
current pulses needed by the gate driver. If an extremely long
risetime is exhibited by the turn on of the FETs, the extra high
frequency capacitance will help.
GENERAL LAYOUT
Good high frequency PC layout techniques are a must. Traces
wide enough for the current delivered, and placement of the big
capacitors close to the MSK 4300 are very important. The
path for the RSENSE connection through any sense resistor
back to the GND pins must be as short as possible. This path is
the gate drive current path for all the FETs on the lower half of
each phase. A short, low inductance path will aid in the switch-
ing time of those FETs.
IN
LOW POWER STARTUP
When starting up the circuit utilizing the MSK 4300 for the first
time, it is very important to keep certain things in mind. Be-
cause of the small size of the bridge, there is no internal short
circuit protection and a short circuit will destroy the bridge.
Any required short circuit protection must be built outside the
bridge. Current and voltage limit the power supply feeding the
V+ pins to the bridge, and monitor the current for any signs of
short circuiting, or shoot-through currents. If there are large
current spikes at the beginning of each switching cycle, there
may be shoot through. Try raising the resistor value of the
SWR. This will lengthen the deadtime and stop shoot-through.
Rev. C 6/00
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