Latch-up Current.................................................... > 200 mA
Operating Range
Device
Range
Ambient
Temperature
V
CC
CY62137CV18 Industrial
−40°C
to +85°C 1.65V to 1.95V
Product Portfolio
Power Dissipation (Industrial)
Operating (I
CC
)
V
CC
Range
Product
CY62137CV18
V
CC(min.)
V
CC(typ.)
[4]
1.65V
1.80V
V
CC(max.)
1.95V
Speed
55 ns
70 ns
f = 1 MHz
Typ.
[4]
0.5 mA
0.5 mA
Max.
2 mA
2 mA
f = f
max
Typ.
[4]
2 mA
1.5 mA
Max.
7 mA
6 mA
Standby (I
SB2
)
Typ.
[4]
1
µA
Max.
8
µA
Electrical Characteristics
Over the Operating Range
CY62137CV18-55
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current GND < V
I
< V
CC
Test Conditions
I
OH
=
−0.1
mA
I
OL
= 0.1 mA
V
CC
= 1.65V
V
CC
= 1.65V
1.4
–0.2
–1
Min.
1.4
0.2
V
CC
+
0.2V
0.4
+1
1.4
–0.2
–1
Typ.
[4]
Max.
CY62137CV18-70
Min. Typ.
[4]
Max. Unit
1.4
0.2
V
CC
+
0.2V
0.4
+1
V
V
V
V
µA
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or V
SS
to ensure proper application.
3. V
IL
(min) =
−2.0V
for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
Document #: 38-05017 Rev. *C
Page 2 of 11
CY62137CV18 MoBL2™
Electrical Characteristics
Over the Operating Range
(continued)
CY62137CV18-55
Parameter
I
OZ
Description
Output Leakage
Current
V
CC
Operating Supply
Current
Test Conditions
GND < V
O
< V
CC
, Output Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
V
CC
= 1.95V
I
OUT
= 0 mA
CMOS levels
Min. Typ.
[4]
–1
2
0.5
1
Max.
+1
7
2
8
CY62137CV18-70
Min. Typ.
[4]
Max. Unit
–1
1.5
0.5
1
+1
6
2
8
µA
mA
mA
µA
I
CC
I
SB1
Automatic CE
CE > V
CC
−
0.2V, V
IN
> V
CC
−
0.2V, V
IN
Power-down Current— < 0.2V f = f
MAX
(Address and Data
Only), f = 0 (OE, WE, BHE, and BLE)
CMOS Inputs
Automatic CE
CE > V
CC
−
0.2V V
IN
> V
CC
−
0.2V or
Power-down Current— V
IN
< 0.2V, f = 0, V
CC
= 1.95V
CMOS Inputs
I
SB2
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
6
8
Unit
pF
pF
Thermal Resistance
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
[5]
Thermal Resistance
(Junction to Case)
[5]
Test Conditions
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board
BGA
55
16
Unit
°C/W
°C/W
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
GND
30 pF
INCLUDING
JIG AND
SCOPE
R2
Rise Time:
1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
RTH
ALL INPUT PULSES
V
CC
Typ
10%
90%
90%
10%
Fall Time:
1 V/ns
OUTPUT
V
Parameters
R1
R2
R
TH
V
TH
1.8V
13500
10800
6000
0.80
UNIT
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.0V, CE > V
CC
−
0.2V,
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V
Conditions
Min.
1.0
0.5
Typ.
[4]
Max.
1.95
5
Unit
V
µA
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05017 Rev. *C
Page 3 of 11
CY62137CV18 MoBL2™
Data Retention Characteristics
(Over the Operating Range) (continued)
Parameter
t
CDR[5]
t
R[6]
Description
Chip Deselect to Data
Retention Time
Operation Recovery Time
Conditions
Min.
0
t
RC
Typ.
[4]
Max.
Unit
ns
ns
Data Retention Waveform
[7]
DATA RETENTION MODE
V
CC
V
CC(min.)
t
CDR
V
DR
> 1.0 V
V
CC(min.)
t
R
CE or
BHE.BLE
Switching Characteristics
Over the Operating Range
[8]
55 ns
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
Cycle
[11]
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
55
40
40
0
0
40
40
25
0
70
60
60
0
0
50
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to
OE HIGH to
Low-Z
[9]
High-Z
[9, 10]
5
20
0
55
55
5
20
5
25
0
70
70
5
20
10
25
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
70 ns
Max.
Unit
CE LOW to Low-Z
[9]
CE HIGH to High-Z
[9, 10]
CE LOW to Power-up
CE HIGH to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to
Low-Z
[9]
[9, 10]
BLE/BHE HIGH to High-Z
Notes:
6. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100
µs
or stable at V
CC(min)
> 100
µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ)
/2, input pulse levels of 0 to V
CC(typ)
, and output loading of the
specified I
OL
/I
OH
and 30 pF load capacitance.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. t
HZOE
, t
HZCE
, t
HZBE
and t
HZWE
transitions are measured when the outputs enter a high impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE =V
IL
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
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