MBM29SL160TD datasheet, PDF - EEWORLD Datasheet

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MBM29SL160TD: Description16M (2M x 8/1M x 16) BIT; File Size358KB，61 Pages; ManufacturerFUJITSU; Websitehttp://edevice.fujitsu.com/fmd/en/index.html

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MBM29SL160TD Overview

16M (2M x 8/1M x 16) BIT

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20877-1E

FLASH MEMORY

CMOS

16M (2M

8/1M

16) BIT

MBM29SL160TD

-10/-12

/MBM29SL160BD

-10/-12

FEATURES

• Single 1.8 V read, program, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)

48-ball FBGA (Package suffix: PBT)

• Minimum 100,000 program/erase cycles

• High performance

100 ns maximum access time

• Sector erase architecture

Eight 4K word and thirty one 32K word sectors in word mode

Eight 8K byte and thirty one 64K byte sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• One Time Protect (OTP) region

256 Byte of OTP accessible through a new “OTP Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC input pin

At V

, allows protection of boot sectors, regardless of sector protection/unprotection status

At V

, allows removal of boot sector protection

At V

, increases program performance

• Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program

Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

(Continued)

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

MBM29SL160TD

-10/-12

/MBM29SL160BD

-10/-12

GENERAL DESCRIPTION

The MBM29SL160TD/BD are a 16M-bit, 1.8 V-only Flash memory organized as 2M bytes of 8 bits each or 1M

words of 16 bits each. The MBM29SL160TD/BD are offered in a 48-pin TSOP(I) and 48-ball FBGA Package.

These devices are designed to be programmed in-system with the standard system 1.8 V V

supply. 12.0 V

and 5.0 V V

are not required for write or erase operations. The devices can also be reprogrammed in

standard EPROM programmers.

The standard MBM29SL160TD/BD offer access times 100 ns and 120 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),

write enable (WE), and output enable (OE) controls.

The MBM29SL160TD/BD are pin and command set compatible with JEDEC standard E

PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents serve as

input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the devices

is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29SL160TD/BD are programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.7 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the devices automatically time the erase pulse widths and

verify proper cell margin.

A sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29SL160TD/BD are erased when shipped from the

factory.

The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the devices internally reset to the read mode.

Fujitsu’s Flash technology combines years of EPROM and E

PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The MBM29SL160TD/BD memories electrically erase the entire chip

or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one

byte/word at a time using the EPROM programming mechanism of hot electron injection.

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