D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
CY2318BNZ
18 Output, 3.3V SDRAM Buffer for
Desktop PCs with 4 DIMMs
Features
• One input to 18 output buffer/driver
• Supports up to four SDRAM DIMMs
• Two additional outputs for feedback
• SMBus interface for individual output control
• Low skew outputs (< 200 ps)
• Up to 100 MHz operation for Industrial temperatures
• Up to 133 MHz operation for Commercial temperatures
• Dedicated OE pin for testing
• Space-saving 48-pin SSOP package
• 3.3V operation
Functional Description
The CY2318BNZ is a 3.3V buffer designed to distribute
high-speed clocks in PC applications. The part has 18 outputs,
16 of which can be used to drive up to four SDRAM DIMMs,
and the remaining can be used for external feedback to a PLL.
The device operates at 3.3V and outputs can run up to 100
MHz, thus making it compatible with Pentium II
®
processors.
The CY2318BNZ can be used in conjunction with the CY2280,
CY2281, CY2282 or similar clock synthesizer for a complete
Pentium II motherboard solution.
The CY2318BNZ also includes an SMBus interface which can
enable or disable each output clock. On power-up, all output
clocks are enabled (internal pull up). A separate Output Enable
pin facilitates testing on ATE.
Block Diagram
Pin Configuration
SSOP
Top View
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM13
SDRAM14
SDRAM15
SDRAM16
SDRAM17
OE
SDATA
SMBus
Decoding
SCLOCK
NC
NC
V
DD
SDRAM0
SDRAM1
V
SS
V
DD
SDRAM2
SDRAM3
V
SS
BUF_IN
V
DD
SDRAM4
SDRAM5
V
SS
V
DD
SDRAM6
SDRAM7
V
SS
V
DD
SDRAM16
V
SS
V
DDIIC
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
V
DD
SDRAM15
SDRAM14
V
SS
V
DD
SDRAM13
SDRAM12
V
SS
OE
V
DD
SDRAM11
SDRAM10
V
SS
V
DD
SDRAM9
SDRAM8
V
SS
V
DD
SDRAM17
V
SS
V
SSIIC
SCLOCK
Pentium II is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07217 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 4, 2001
CY2318BNZ
Pin Summary
Name
V
DD
V
SS
V
DDIIC
V
SSIIC
BUF_IN
OE
SDATA
SCLK
SDRAM [0–3]
SDRAM [4–7]
SDRAM [8–11]
SDRAM [12–15]
SDRAM [16–17]
N/C
Pins
3, 7, 12, 16, 20, 29, 33, 37, 42, 46
23
26
11
38
24
25
4, 5, 8, 9
13, 14, 17, 18
31, 32, 35, 36
40, 41, 44, 45
21, 28
1, 2, 47, 48
Description
3.3V Digital voltage supply
SMBus Voltage supply
Ground for SMBus
Input clock (5V tolerant)
Output Enable (active HIGH), Three-state outputs when LOW
[1]
SMBus data input
[1]
SMBus clock input
[1]
SDRAM byte 0 clock outputs
SDRAM byte 1 clock outputs
SDRAM byte 2 clock outputs
SDRAM byte 3 clock outputs
SDRAM clock outputs usable for feedback
Reserved for future modifications, do not connect in system
6, 10, 15, 19, 22, 27, 30, 34, 39, 43 Ground
Note:
1. Internal pull-up resistor to V
DD
(value > 100 kohms).
Device Functionality
OE
0
1
SDRAM [0–17]
Hi-Z
1 x BUF_IN
Document #: 38-07217 Rev. **
Page 2 of 8
CY2318BNZ
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• SMBus Address for the CY2318BNZ is:
•
•
Byte 1: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
45
44
41
40
36
35
32
31
Description
SDRAM15 (Active/Inactive)
SDRAM14 (Active/Inactive)
SDRAM13 (Active/Inactive)
SDRAM12 (Active/Inactive)
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
A6
1
•
•
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Byte 0:SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Byte 2: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
28
21
--
--
--
--
--
--
Description
SDRAM17 (Active/Inactive)
SDRAM16 (Active/Inactive)
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
Bit 7 18
Bit 6 17
Bit 5 14
Bit 4 13
Bit 3 9
Bit 2 8
Bit 1 5
Bit 0 4
Maximum Ratings
Supply Voltage to Ground Potential ..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN) .......... –0.5V to V
DD
+ 0.5
DC Input Voltage (BUF_IN).............................. –0.5V to 7.0V
Storage Temperature .................................–65
°
C to +150
°
C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)..............................>2000V
Ambient Temperature under BIAS ..............–55
°
C to +125
°
C
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
Description
Voltage on Any Pin with Respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
Unit
V
°C
°C
°C
Operating Conditions
Parameter
V
DD
, V
DDIIC
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min.
3.135
–40
20
Max.
3.465
85
30
7
Unit
V
°C
pF
pF
Page 3 of 8
Document #: 38-07217 Rev. **
CY2318BNZ
DC Electrical Characteristics:
T
A
= -40°C to +85°C, V
DDQ3
= 3.3V±5%
Parameter
I
DD
I
DD Tristate
V
IL
V
IH
I
ILEAK
I
ILEAK
V
OL
V
OH
I
OL
I
OH
C
IN
C
OUT
L
IN
Description
3.3V Supply Current
3.3V Supply Current in Three-state
Input Low Voltage
Input High Voltage
Input Leakage Current, BUF_IN
Input Leakage Current
[2]
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Input Pin Capacitance (Except
BUF_IN)
Output Pin Capacitance
Input Pin Inductance
I
OL
= 1 mA
I
OH
= –1 mA
V
OL
= 1.5V
V
OH
= 1.5V
3.1
70
65
110
100
185
160
5
6
7
Test Condition/
Comments
BUF_IN = 64 MHz
BUF_IN = 100 MHz
GND–0.3
2.0
–5
–20
Min
140
Typ
165
5
0.8
V
DDQ3
+ 0.5
+5
+5
50
Max
200
Unit
mA
mA
V
V
µA
µA
mV
V
mA
mA
pF
pF
nH
Logic Inputs (BUF_IN, OE, SCLOCK, SDATA)
Logic Outputs (SDRAM0:17)
[3]
Pin Capacitance/Inductance
Document #: 38-07217 Rev. **
Page 4 of 8
京公网安备 11010802033920号
EEWORLD
