INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4021B
MSI
8-bit static shift register
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
8-bit static shift register
DESCRIPTION
The HEF4021B is an 8-bit static shift register
(parallel-to-serial converter) with a synchronous serial
data input (D
S
), a clock input (CP), an asynchronous active
HIGH parallel load input (PL), eight asynchronous parallel
data inputs (P
0
to P
7
) and buffered parallel outputs from
the last three stages (0
5
to O
7
).
HEF4021B
MSI
Each register stage is a D-type master-slave flip-flop with
a set direct/clear direct input. Information on P
0
to P
7
is
asynchronously loaded into the register while PL is HIGH,
independent of CP and DS. When PL is LOW, data on
D
S
is shifted into the first register position and all the data
in the register is shifted one position to the right on the
LOW to HIGH transition of CP. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
Fig.1 Functional diagram.
HEF4021BP(N):
HEF4021BD(F):
HEF4021BT(D):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
PINNING
PL
P
0
to P
7
D
S
CP
O
5
to O
7
parallel load input
parallel data inputs
serial data input
clock input (LOW to HIGH edge-triggered)
buffered parallel outputs from the last three stages
January 1995
2
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Philips Semiconductors
January 1995
8-bit static shift register
3
Product specification
HEF4021B
MSI
Fig.3 Logic diagram.
Philips Semiconductors
Product specification
8-bit static shift register
FUNCTION TABLES
Serial operation
INPUTS
n
1
2
3
6
7
8
CP
D
S
D
1
D
2
D
3
X
X
X
X
PL
L
L
L
L
L
L
L
O
5
X
X
X
D
1
D
2
D
3
OUTPUTS
O
6
X
X
X
X
D
1
D
2
no change
O
7
X
X
X
X
X
D
1
Notes
n
CP
X
HEF4021B
MSI
Parallel operation
INPUTS
D
S
X
PL
H
O
5
P
5
OUTPUTS
O
6
P
6
O
7
P
7
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
D
n
= either HIGH or LOW
n = number of clock pulse transitions
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
CP
→
O
n
HIGH to LOW
5
10
15
5
LOW to HIGH
PL
→
O
n
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
Output transition
times
HIGH to LOW
LOW to HIGH
10
15
5
10
15
5
10
15
t
TLH
t
THL
t
PLH
t
PHL
t
PLH
t
PHL
125
55
40
115
50
40
120
55
40
105
50
40
60
30
20
60
30
20
250
110
80
230
100
80
240
110
80
210
100
80
120
60
40
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
98 ns
+
(0,55 ns/pF) C
L
44 ns
+
(0,23 ns/pF) C
L
32 ns
+
(0,16 ns/pF) C
L
88 ns
+
(0,55 ns/pF) C
L
39 ns
+
(0,23 ns/pF) C
L
32 ns
+
(0,16 ns/pF) C
L
93 ns
+
(0,55 ns/pF) C
L
44 ns
+
(0,23 ns/pF) C
L
32 ns
+
(0,16 ns/pF) C
L
78 ns
+
(0,55 ns/pF) C
L
39 ns
+
(0,23 ns/pF) C
L
32 ns
+
(0,16 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
January 1995
4
Philips Semiconductors
Product specification
8-bit static shift register
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Set-up time
D
S
→
CP
5
10
15
5
P
n
→
PL
Hold times
D
S
→
CP
10
15
5
10
15
5
P
n
→
PL
Minimum clock
pulse width; LOW
Minimum PL
pulse width; HIGH
Recovery time
for PL
Maximum clock
pulse frequency
10
15
5
10
15
5
10
15
5
10
15
5
10
15
f
max
t
RPL
t
WPLH
t
WCPL
t
hold
t
hold
t
su
t
su
SYMBOL
MIN.
25
25
15
50
30
20
40
20
15
15
15
15
70
30
24
70
30
24
50
40
35
6
15
20
TYP.
−15
−10
−5
25
10
5
20
10
8
−10
0
0
35
15
12
35
15
12
10
5
5
13
30
40
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
HEF4021B
MSI
see also waveforms
Figs 4 and 5
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
900 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
4 300 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
12 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
5
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