EPF8820AQC208-3N datasheet, PDF

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EPF8820AQC208-3N: DescriptionLoadable PLD, CMOS, PQFP208, PLASTIC, QFP-208; CategoryProgrammable logic devices Programmable logic; File Size904KB，62 Pages; ManufacturerAltera (Intel); Environmental Compliance

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EPF8820AQC208-3N Overview

Loadable PLD, CMOS, PQFP208, PLASTIC, QFP-208

EPF8820AQC208-3N Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Altera (Intel)
Parts packaging code	QFP
package instruction	FQFP,
Contacts	208
Reach Compliance Code	compliant
Other features	672 LOGIC ELEMENTS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
JESD-30 code	S-PQFP-G208
JESD-609 code	e3
length	28 mm
Humidity sensitivity level	3
Dedicated input times	4
Number of I/O lines	152
Number of terminals	208
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4 DEDICATED INPUTS, 152 I/O
Output function	REGISTERED
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	245
Programmable logic type	LOADABLE PLD
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN (472) OVER COPPER
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	28 mm
Base Number Matches	1

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FLEX 8000

Programmable Logic

Device Family

Data Sheet

January 2003, ver. 11.1

Features...

■

Low-cost, high-density, register-rich CMOS programmable logic

device (PLD) family (see

Table 1)

–

2,500 to 16,000 usable gates

–

282 to 1,500 registers

System-level features

– In-circuit reconfigurability (ICR) via external configuration

devices or intelligent controller

– Fully compliant with the peripheral component interconnect

Special Interest Group (PCI SIG)

PCI Local Bus Specification,

Revision 2.2

for 5.0-V operation

– Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)

circuitry compliant with IEEE Std. 1149.1-1990 on selected devices

– MultiVolt

I/O interface enabling device core to run at 5.0 V,

while I/O pins are compatible with 5.0-V and 3.3-V logic levels

– Low power consumption (typical specification is 0.5 mA or less in

standby mode)

Flexible interconnect

– FastTrack

Interconnect continuous routing structure for fast,

predictable interconnect delays

– Dedicated carry chain that implements arithmetic functions such

as fast adders, counters, and comparators (automatically used by

software tools and megafunctions)

– Dedicated cascade chain that implements high-speed, high-fan-in

logic functions (automatically used by software tools and

megafunctions)

– Tri-state emulation that implements internal tri-state nets

Powerful I/O pins

Programmable output slew-rate control reduces switching noise

FLEX 8000

Table 1. FLEX 8000 Device Features

Feature

Usable gates

Flipflops

Logic array blocks (LABs)

Logic elements (LEs)

Maximum user I/O pins

EPF8282A

EPF8282AV

2,500

282

208

EPF8452A

4,000

452

336

120

EPF8636A

6,000

636

504

136

EPF8820A

8,000

820

672

152

EPF81188A EPF81500A

12,000

1,188

126

1,008

184

16,000

1,500

162

1,296

208

Altera Corporation

DS-F8000-11.1

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