PCI Express Jitter Attenuator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
Data Sheet
9DB206
G
ENERAL
D
ESCRIPTION
The 9DB206 is a high perfromance 1-to-6 Differential-to-HCSL
Jitter Attenuator designed for use in PCI Express™ systems. In
some PCI Express systems, such as those found in desktop PCs,
the PCI Express clocks are generated from a low bandwidth,
high phase noise PLL frequency synthesizer. In these systems, a
jitter-attenuating device may be necessary in order to reduce high
frequency random and deterministic jitter components from the PLL
synthesizer and from the system board. The 9DB206 has two PLL
bandwidth modes. In low bandwidth mode, the PLL loop bandwidth
is 500kHz. This setting offers the best jitter attenuation and is still
high enough to pass a triangular input spread spectrum profile. In
high bandwidth mode, the PLL bandwidth is at 1MHz and allows
the PLL to pass more spread spectrum modulation.
For serdes which have x10 reference multipliers instead of x12.5
multipliers, 5 of the 6 PCI Express outputs (PCIEX1:5) can be set
for 125MHz instead of 100MHz by configuring the appropriate
frequency select pins (FS0:1). Output PCIEX0 will always run at
the reference clock frequency (usually 100MHz) in desktop PC PCI
Express Applications.
Features
•
Six 0.7V current mode differential HCSL output pairs
•
One differential clock input
•
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 140MHz
•
Input frequency range: 90MHz - 140MHz
•
VCO range: 450MHz - 700MHz
•
Output skew: 110ps (maximum)
•
Cycle-to-Cycle jitter: 110ps (maximum)
•
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
2.42ps (typical)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Available in lead-free RoHS compliant package
•
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
IREF
-
+
Current
Set
1 HiZ
0 Enabled
÷5
PCIEXT0
nPCIEXC0
P
IN
A
SSIGNMENT
PLL_BW
CLK
nCLK
FS0
PCIEXT0
PCIEXC0
V
DD
GND
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
V
DD
nOE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DDA
GND
IREF
FS1
PCIEXT5
PCIEXC5
V
DD
GND
PCIEXT4
PCIEXC4
PCIEXT3
PCIEXC3
V
DD
nOE1
nOE0
nCLK
CLK
Phase
Detector
Loop
Filter
VCO
0 ÷4
1 ÷5
PCIEXT1
nPCIEXC1
PCIEXT2
nPCIEXC2
÷5
Internal Feedback
FS0
9DB206
0 ÷5
1 ÷4
PCIEXT3
nPCIEXC3
PCIEXT4
nPCIEXC4
PCIEXT5
nPCIEXC5
28-Lead TSSOP, 173-MIL
4.4mm x 9.7mm x 0.92mm body package
L Package
Top View
9DB206
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm body package
F Package
Top View
FS1
nOE1
1 HiZ
0 Enabled
©2016 Integrated Device Technology, Inc
1
Revision B March 11, 2016
9DB206 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5, 6
7, 13, 16, 22
8, 21
9, 10
11, 12
14, 15
17, 18
19, 20
23, 24
25
26
27
28
Name
PLL_BW
CLK
nCLK
FS0
PCIEXT0,
PCIEXC0
V
DD
GND
PCIEXT1,
PCIEXC1
PCIEXT2,
PCIEXC2
nOE0, nOE1
PCIEXC3,
PCIEXT3
PCIEXC4,
PCIEXT4
PCIEXC5,
PCIEXT5
FS1
IREF
GND
V
DDA
Input
Input
Input
Input
Output
Power
Power
Output
Output
Input
Output
Output
Output
Input
Input
Power
Power
Pulldown
Type
Pullup
Description
Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
Pulldown Non-inverting differential clock input.
Pullup/
Inverting differential clock input. V /2 default when left floating.
Pulldown
DD
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
Differential output pairs. HCSL interface levels.
Core supply pins.
Power supply ground.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Output enable. When HIGH, forces outputs to HiZ state.
When LOW, enables outputs. LVCMOS/LVTTL interface levels.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
A fixed precision resistor (475
Ω
) from this pin to ground provides a refer-
ence current used for differential current-mode PCIEX clock outputs.
Power supply ground.
Analog supply pin. Requires 24
Ω
series resistor.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. R
ATIO OF
O
UTPUT
F
REQUENCY TO
I
NPUT
F
REQUENCY
F
UNCTION
T
ABLE
, FS0
Inputs
FS0
0
1
PCIEX0
1
1
Outputs
PCIEX1
5/4
1
PCIEX2
5/4
1
T
ABLE
3B. R
ATIO OF
O
UTPUT
F
REQUENCY TO
I
NPUT
F
REQUENCY
F
UNCTION
T
ABLE
, FS1
Inputs
FS1
0
1
PCIEX3
1
5/4
Outputs
PCIEX4
1
5/4
PCIEX5
1
5/4
T
ABLE
3C. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
, nOE0
Inputs
nOE0
0
1
Outputs
PCIEX0:2
Enabled
HiZ
T
ABLE
3D. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
, nOE1
Inputs
nOE1
0
1
Outputs
PCIEX3:5
Enabled
HiZ
T
ABLE
3E. PLL B
ANDWIDTH
T
ABLE
Inputs
PLL_BW
0
1
Bandwidth
500kHz
1MHz
©2016 Integrated Device Technology, Inc
2
Revision B March 11, 2016
9DB206 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
28 Lead TSSOP
28 Lead SSOP
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
49.8°C/W (0 lfpm)
49°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C, RREF = 475Ω
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
112
22
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
FS1, nOE0, nOE1
FS0, PLL_BW
FS1, nOE0, nOE1
FS0, PLL_BW
V
DD
= 3.465V, V
IN
= 0V
-5
-150
V
DD
= V
IN
= 3.465V
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
mV
mV
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C, RREF = 475Ω
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK, nCLK
CLK, nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
0.15
GND + 0.5
Minimum
Typical
Maximum
150
150
1.3
V
DD
- 0.85
Units
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
©2016 Integrated Device Technology, Inc
3
Revision B March 11, 2016
9DB206 Data Sheet
T
ABLE
4D. HCSL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C, RREF = 475Ω
Symbol
I
OH
Parameter
Output Current
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Crossover Voltage
Test Conditions
Minimum
12
610
-10
250
Typical
14
Maximum
16
780
65
10
550
Units
mA
mV
mV
µA
mV
V
V
I
V
OH
OL
OZ
OX
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C, RREF = 475Ω
Symbol
f
Parameter
Output Frequency
Output Skew; NOTE 1, 2
Cycle-to-Cycle Jitter
RMS Phase Jitter (Ran-
dom); NOTE 3
Output Rise/Fall Time
Output Duty Cycle
Outputs @ Different Frequencies
Outputs @ Same Frequencies
Integration Range: 1.5MHz - 22MHz
20% to 80%
300
48
2.42
1100
52
50
Test Conditions
Minimum
Typical
Maximum
140
110
110
50
Units
MHz
ps
ps
ps
ps
ps
%
t
sk(o)
t
jit(cc)
t
jit(Ø)
t /t
R
F
MAX
odc
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot following this section.
©2016 Integrated Device Technology, Inc
4
Revision B March 11, 2016
9DB206 Data Sheet
T
YPICAL
P
HASE
N
OISE AT
100MH
Z
0
-10
-20
-30
-40
-50
-60
➤
PCI Express™ Filter
100MHz
RMS Phase Jitter (Random)
1.5MHz to 22MHz = 2.42ps (typical)
N
OISE
P
OWER
dBc
Hz
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
Raw Phase Noise Data
➤
The illustrated phase noise plot was taken using a low phase noise
signal generator, the noise floor of the signal generator is less than
that of the device under test.
Using this configuration allows one to see the true spectral purity or
phase noise performance of the PLL in the device under test. Due
➤
Phase Noise Result by adding
PCI Express™ Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
to the tracking ability of a PLL, it will track the input signal up to its
loop bandwidth. Therefore, if the input phase noise is greater than
that of the PLL, it will increase the output phase noise performance
of the device. It is recommended that the phase noise performance
of the input is verified in order to achieve the above phase noise
performance.
©2016 Integrated Device Technology, Inc
5
Revision B March 11, 2016
Analogue and Mixed Signal
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