DATASHEET
4 OUTPUT PCIE GEN1/2 SYNTHESIZER
Recommended Applications
4 Output synthesizer for PCIe Gen1/2
IDT5V41186
Features/Benefits
•
20-pin TSSOP package; small board footprint
•
Spread-spectrum capable; reduces EMI
•
Outputs can be terminated to LVDS; can drive a wider
variety of devices
General Description
The IDT5V41186 is a PCIe Gen2 compliant
spread-spectrum-capable clock generator. The device has
4 differential HCSL outputs and can be used in
communication or embedded systems to substantially
reduce electro-magnetic interference (EMI). The spread
amount and output frequency are selectable via select pins.
•
Power down pin; greater system power management
•
OE control pin; greater system power management
•
Spread% and frequency pin selection; no software
required to configure device
•
Industrial temperature range available; supports
demanding embedded applications
Output Features
•
4 - 0.7V current mode differential HCSL output pairs
•
For PCIe Gen3 applications, see the 5V41236
Key Specifications
•
Cycle-to-cycle jitter < 100 ps
•
Output-to-output skew < 50 ps
•
PCIe Gen2 phase jitter < 3.0ps RMS
Block Diagram
VDD
2
PD
OE
3
SEL[2:0]
Spread
Spectrum/
Output
clock
selection
Spread
Spectrum
Circuitry
CLKOUTA
X1
25 MHz
crystal or
clock
Clock
Oscillator
X2
CLKOUTA
CLKOUTB
PLL Clock
Synthesis
CLKOUTB
CLKOUTC
CLKOUTC
CLKOUTD
CLKOUTD
2
GND
Rr(IREF)
Optional tuning crystal
capacitors
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4 OUTPUT PCIE GEN1/2 SYNTHESIZER
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4 OUTPUT PCIE GEN1/2 SYNTHESIZER
Pin Assignment
VDDXD
S0
S1
S2
X1
X2
PD
OE
GNDXD
IREF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLKA
CLKA
CLKB
CLKB
GNDODA
VDDODA
CLKC
CLKC
CLKD
CLKD
20-pin (173 mil) TSSOP
Spread Spectrum Selection Table
S2 S1 S0 Spread% Spread Type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-0.5
Down
-1.0
Down
-1.5
Down
No Spread Not Applicable
-0.5
Down
-1.0
Down
-1.5
Down
No Spread Not Applicable
Output
Frequency
100
100
100
100
200
200
200
200
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Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
VDDXD
S0
S1
S2
X1
X2
PD
OE
GND
IREF
CLKD
CLKD
CLKC
CLKC
VDDODA
GND
CLKB
CLKB
CLKA
CLKA
Pin
Type
Power
Input
Input
Input
Input
Output
Input
Input
Power
Output
Output
Output
Output
Output
Power
Power
Pin Description
Connect to +3.3 V digital supply.
Spread spectrum select pin #0. See table above. Internal pull-up resistor.
Spread spectrum select pin #1. See table above Internal pull-up resistor.
Spread spectrum select pin #2. See table above. Internal pull-up resistor.
Crystal connection. Connect to a fundamental mode crystal or clock input.
Crystal connection. Connect to a fundamental mode crystal or leave open.
Powers down all PLL’s and tri-states outputs when low. Internal pull-up resistor.
Provides output on, tri-states output (High = enable outputs; Low = disable outputs).
Internal pull-up resistor.
Connect to digital ground.
Precision resistor attached to this pin is connected to the internal current reference.
Selectable 100/200 MHz spread spectrum differential Complement output clock D.
Selectable 100/200 MHz spread spectrum differential True output clock D.
Selectable 100/200 MHz spread spectrum differential Complement output clock C.
Selectable 100/200 MHz spread spectrum differential True output clock C.
Connect to +3.3 V analog supply.
Connect to analog ground.
Output Selectable 100/200 MHz spread spectrum differential Complement output clock B.
Output Selectable 100/200 MHz spread spectrum differential True output clock B.
Output Selectable 100/200 MHz spread spectrum differential Complement output clock A.
Output Selectable 100/200 MHz spread spectrum differential True output clock A.
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Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
IDT5V41186 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Load Resistors R
L
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41186 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the
PCI-Express Layout Guidelines
section.
The IDT5V41186 can also be configured for LVDS
compatible voltage levels. See the
LVDS Compatible
Layout Guidelines
section.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the IDT5V41186.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01F should
be connected between VDD and GND pairs (1,9 and 15,16)
as close to the device as possible.
On chip capacitors-
Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (C
L
-12)*2 in this equation, C
L
=crystal
load capacitance in pf. For example, for a crystal with a 16
pF load cap, each external crystal cap would be 8 pF.
[(16-12)x2]=8.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50, then Rr = 475
(1%), providing IREF of 2.32 mA, output current (I
OH
) is
equal to 6*IREF.
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Output Structures
IREF
=2.3 mA
6*IREF
R
R
475
See Output Termination
Sections - Pages 6~8
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41186.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
IDT®
4 OUTPUT PCIE GEN1/2 SYNTHESIZER
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