IS25WQ080
8 Mbit bit Single Operating Voltage Serial Flash Memory With 104 MHz
Dual- or Quad-Output SPI Bus Interface
FEATURES
• Single Power Supply Operation
- Low voltage range: 1.65 V – 1.95 V
• Memory Organization
- IS25WQ080: 1024K x 8 (8 Mbit)
• Cost Effective Sector/Block Architecture
- 8Mb : Uniform 4KByte sectors / Sixteen uniform
64KByte blocks
• Serial Peripheral Interface (SPI) Compatible
- Supports single-, dual- or quad-output
- Supports SPI Modes 0 and 3
- Maximum 33 MHz clock rate for normal read
- Maximum 104 MHz clock rate for fast read
- Maximum 208MHz clock rate equivalent Dual SPI
- Maximum 416MHz clock rate equivalent Quad SPI
•
Byte Program Operation
- Typical 8 us/Byte
•
Page Program (up to 256 Bytes) Operation
- Maximum 0.7 ms per page program
• Sector, Block or Chip Erase Operation
- Sector Erase (4KB)150 ms (Max)
- Block Erase
(32K/64KB)0.5S
(Max)
- Chip Erase
6s
(8Mb) (Max)
•Deep power-down mode 1uA (Typ)
PRELIMINARY DATASHEET
• Low Power Consumption
- Max 15 mA active read current
- Max 20 mA program/erase current
-
Max 50uA standby current
• Hardware Write Protection
- Protect and unprotect the device from write
operation by Write Protect (WP#) Pin
• Software Write Protection
-
The Block Protect (BP3, BP2, BP1, BP0) bits
allow partial or entire memory to be configured as
read-only
• High Product Endurance
- Guaranteed 100,000 program/erase cycles per
single sector
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin SOIC 208mil
- 8-pin SOIC 150mil
- 8-pin VVSOP 150mil
- 8-pin WSON (5x6mm)
- Lead-free (Pb-free) package
Additional 256-byte Security information one-
time programmable (OTP) area
GENERAL DESCRIPTION
The IS25WQ080 are 8Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or quad-
output. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104 MHz in fast
read, the fastest in the industry. The devices use a single low voltage power supply, ranging from 1.65 Volt to
1.95 Volt, to perform read, erase and program operations. The devices can be programmed in standard EPROM
programmers.
The IS25WQ080 are accessed through a 4-wire SPI Interface consisting of Serial Data Input (Sl), Serial Data
Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program mode, where
1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided
into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks.
The IS25WQ080 are manufactured on pFLASH™’s advanced non-volatile technology.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0B
02/28/2013
1
IS25WQ080
PIN DESCRIPTIONS
SYMBOL
CE#
TYPE
INPUT
DESCRIPTION
Chip Enable: CE# low activates the devices internal circuitries for
device operation. CE# high deselects the devices and switches into
standby mode to reduce the power consumption. When a device is not
selected, data will not be accepted via the serial input pin (Sl), and the
serial output pin (SO) will remain in a high impedance state.
Serial Data Clock
Serial Data Input/Output
Serial Data Input/Output
Ground
Device Power Supply
Write Protect/Serial Data Output: A hardware program/erase protection for all or
part of a memory array. When the WP# pin is low, memory array write-protection
depends on the setting of BP3, BP2, BP1 and BP0 bits in the Status Register.
When the WP# is high, the status register are not write-protected.
When the QE bit of is set “1”, the /WP pin (Hardware Write Protect) function is
not available since this pin is used for IO2
Hold: Pause serial communication by the master device without resetting
the serial sequence.
When the QE bit of Status Register-2 is set for “1”, the function is Serial Data
Input & Output (for 4xI/O read mode)
SCK
SI (IO0)
SO (IO1)
GND
Vcc
WP#
(IO2)
INPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
HOLD#
(IO3)
INPUT/OUTPUT
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0B
02/28/2013
3
IS25WQ080
SPI MODES DESCRIPTION
Multiple IS25WQ080 devices can be connected on the
SPI serial bus and controlled by a SPI Master, i.e.
microcontroller, as shown in Figure 1. The devices
support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and
the clock remains at “1” (SCK = 1) for Mode 3. Please
refer to Figure 2. For both modes, the input data is
latched on the rising edge of Serial Clock (SCK), and
the output data is available from the falling edge of
SCK.
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDI
SPI Interface with
(0,0) or (1,1)
SDI
SCK
SCK
SPI Master
(i.e. Microcontroller)
CS3
CS2
CS1
CE#
SO
SI
SCK
SO
SI
SCK
SO
SI
SPI Memory
Device
SPI Memory
Device
SPI Memory
Devic
e
CE#
WP#
HOLD#
WP#
HOLD#
CE#
WP#
HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as
appropriate.
Figure 2. SPI Modes Supported
SCK
Mode 0 (0,0)
SCK
Mode 3 (1,1)
SI
Input mode
SO
MSb
MSb
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0B
02/28/2013
5
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