LVCMOS Clock Generator
870919I-01
DATA SHEET
General Description
The 870919I-01 is an LVCMOS clock generator that uses an internal
phase lock loop (PLL) for frequency multiplication and to lock the
low-skew outputs to the selected reference clock. The device offers
eight outputs. The PLL loop filter is completely internal and does not
require external components. Several output configurations of the
PLL feedback and a divide-by-2 (controlled by FREQ_SEL) allow
applications to optimize frequency generation over a wide range of
input reference frequencies. The PLL can also be disabled by the
PLL_EN control signal to allow for low frequency or DC testing. The
LOCK output asserts to indicate when phase-lock has been
achieved. The 870919I-01 device is a member of the family of high
performance clock solutions from IDT.
Features
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Two selectable single-ended input reference clocks
Eight single-ended clock outputs
Internal PLL does not require external loop filter components
5V tolerant inputs
Maximum output frequency: 160MHz, (2XQ output)
Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs)
LVCMOS interface levels for all inputs and outputs
PLL disable feature for low-frequency testing
PLL lock output
Selectable synchronization of output to input edge
Output drive capability: ±24mA
Output skew: 300ps (maximum), Q0:Q4
Output skew: 500ps (maximum), all outputs
Full 3.3V supply voltage
Available in lead-free packages
-40°C to 85°C ambient operating temperature
Fully pin and function compatible with the IDT QS5LV919
(including 55, 70, 100, 133 and 160MHz options)
For functional replacement part use 8T49N285
Block Diagram
LOCK
0
1
÷2
0
÷1
÷2
2XQ
Q0
Q1
Q2
SYNC0
SYNC1
REF_SEL
0
1
f
REF
PLL
f
VCO
20MHz - 160MHz
1
FEEDBACK
nPE
PLL_EN
FREQ_SEL
÷4
Q3
Q4
nQ5
Q/2
OE/nRST
870919I-01 REVISION C 11/6/15
1
©2015 Integrated Device Technology, Inc.
870919I-01 DATA SHEET
Pin Assignments
OE/nRST
GND
4
FEEDBACK
GND
nQ5
V
DD
OE/nRST
FEEDBACK
REF_SEL
SYNC0
AV
DD
nPE
AGND
SYNC1
FREQ_SEL
GND
Q0
3
2
1
28 27 26
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12 13 14 15 16 17 18
GND
FREQ_SEL
GND
PLL_EN
Q0
V
DD
Q1
2XQ
nQ5
V
DD
Q4
V
DD
Q/2
GND
Q3
V
DD
Q2
GND
LOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Q4
V
DD
2XQ
Q/2
GND
Q3
V
DD
Q2
GND
LOCK
PLL_EN
GND
Q1
V
DD
REF_SEL
SYNC0
AV
DD
nPE
AGND
SYNC1
870919I-01
28-Lead QSOP, 150Mil
3.9mm x 9.9mm x 1.5mm package body
R Package
Top View
870919I-01
28-Lead PLCC
11.5mm x 11.5mm x 4.4mm package body
V Package
Top View
REVISION C 11/6/15
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LVCMOS CLOCK GENERATOR
870919I-01 DATA SHEET
Table 1. Pin Descriptions
Number
1, 13, 17, 20, 24
2
3, 15, 22, 27
Name
GND
nQ5
V
DD
Power
Output
Power
Type
Description
Power supply ground.
Single-ended clock output (phase is inverted with respect to other outputs).
LVCMOS/LVTTL interface levels
Positive power supply pins.
Output enable and asynchronous reset. Resets all outputs. Logic LOW, the
outputs are in a high impedance state. Logic HIGH enables all outputs.
Internally a Power On reset circuit will ensure that the nQ5 output is inverted
relative to Q[4:0]. If OE/nRST is pulsed low, it must be held low for a minimum
of 10 ns for a complete reset operation. This reset may be applied
asynchronously to the input reference.
PLL feedback input which is connected to one of the clock outputs to close the
PLL feedback loop. LVCMOS/LVTTL interface levels.
Input reference clock select. Logic LOW selects the SYNC0.
Logic HIGH selects the SYNC1 input as the PLL reference input.
LVCMOS/LVTTL interface levels.
Single-ended reference clock inputs. LVCMOS/LVTTL interface levels.
Positive power supply for the PLL.
Output phase synchronization. In PLL mode (PLL_EN = HIGH) and when logic
LOW, the rising edges of the outputs (2XQ, Q0:Q4, Q/2) are synchronized to
the rising edge of the selected reference clock (SYNCn).
In PLL mode (PLL_EN = HIGH) and when logic HIGH, the falling edges of the
outputs (2XQ, Q0:Q4, Q/2) are synchronized to the falling edge of the selected
reference clock (SYNCn). LVCMOS/LVTTL interface levels.
Power supply ground for the PLL. Internally connected to GND.
Frequency select. Logic LOW level inserts a divide-by-2 into the PLL output
and feedback path. Logic HIGH inserts a divide-by-1 into the PLL output and
feedback path. LVCMOS/LVTTL interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
PLL enable. Enable and disables the PLL. Logic HIGH enables the PLL. Logic
LOW disables the PLL and the input reference signal is routed to the output
dividers (PLL bypass). LVCMOS/LVTTL interface levels.
PLL lock indication output. Logic HIGH indicates PLL lock. Logic LOW indicates
PLL is not locked. LVCMOS/LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
4
OE/nRST
Input
5
FEEDBACK
Input
6
7,
11
8
REF_SEL
SYNC0,
SYNC1
AVDD
Input
Input
Power
9
nPE
Input
Pulldown
10
12
14, 16,
21, 23, 28
18
AGND
FREQ_SEL
Q0, Q1,
Q2, Q3, Q4
PLL_EN
Power
Input
Output
Input
19
25
26
LOCK
Q/2
2XQ
Output
Output
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
LVCMOS CLOCK GENERATOR
3
REVISION C 11/6/15
870919I-01 DATA SHEET
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance (total)
nPE
V
DD
= AV
DD
= 3.6V
Test Conditions
Minimum
Typical
4
330
56
11
Maximum
Units
pF
pF
k
R
PULLDOWN
Input Pulldown Resistor
R
OUT
Output Impedance
Device Configuration
The 870919I-01 requires a connection of one of the clock outputs to
the FEEDBACK input to close the PLL feedback path. The selection
of the output (output divider) for PLL feedback will impact the device
configuration and input to output frequency ratio and frequency
ranges. See
Table
3G for details.
Function Tables
Table 3A. OE/nRST Mode Configuration Table
Input
OE/nRST
0
1
Operation
Device is reset and the outputs Q0:Q4, nQ5, 2XQ, Q/2 are in high-impedance state. This control is asynchronous.
Outputs are enabled.
Table 3B. REF_SEL Mode Configuration Table
Input
REF_SEL
0
1
Operation
SYNC0 is the selected PLL reference clock.
SYNC1 is the selected PLL reference clock.
Table 3C. nPE Mode Configuration Table
Input
nPE
0
1
Operation
The rising edge of the 2XQ, Q0:Q4 and Q/2 outputs and the falling edge of the nQ5 output are synchronized.
The falling edge of the 2XQ, Q0:Q4 and Q/2 outputs and the rising edge of the nQ5 output are synchronized.
REVISION C 11/6/15
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LVCMOS CLOCK GENERATOR
870919I-01 DATA SHEET
Table 3D. FREQ_SEL Mode Configuration Table
Input
FREQ_SEL
0
1
Operation
The VCO output is frequency-divided by 2. This setting allows for a lower input frequency range.
See also table 3G for available frequency ranges.
The VCO output is frequency-divided by 1. This setting allows for a higher input frequency range.
See also table 3G for available frequency ranges.
Table 3E. PLL_EN Mode Configuration Table
Input
PLL_EN
0
1
Operation
The PLL is bypassed. The selected input reference clock is routed to the output dividers for low-frequency board test
purpose. The PLL-related AC specifications do not apply in PLL bypass mode.
The PLL is enabled and locks to the selected input reference signal.
Table 3F. LOCK Mode Configuration Table
Output
LOCK
0
1
Operation
PLL is not locked to the selected input reference clock.
PLL is locked to the selected input reference clock.
Table 3G. Frequency Configuration Table
Input Frequency Range
(MHz)
FREQ_SEL
0
1
0
2XQ
1
0
Q/2
1
5 - 40
10 - 80 (2x)
20 - 160 (4x)
5 - 40 (1x)
NOTE 1: The nQ5 output is inverted (180° phase shift) with respect to Q0:Q4.
NOTE 2: The input reference frequency is limited to 100MHz maximum.
SYNC[0:1]
5 - 40
10 - 80
10 - 80
20 - 100
NOTE2
2.5 - 20
Output Frequency Range (MHz) and
Output-to-Input Frequency Multiplication Factor
Q[0:4], nQ5
NOTE1
5 - 40 (1x)
10 - 80 (1x)
5 - 40 (0.5x)
10 - 50 (0.5x)
5 - 40 (2x)
2XQ
10 - 80 (2x)
20 - 160 (2x)
10 - 80 (1x)
20 - 100 (1x)
10 - 80 (4x)
Q/2
2.5 - 20 (0.5x)
5 - 40 (0.5x)
2.5 - 20 (0.25x)
5 - 25 (0.25x)
2.5 - 20 (1x)
Outputs Used for
PLL Feedback
Q0, Q1, Q2,
Q3, Q4 or nQ5
LVCMOS CLOCK GENERATOR
5
REVISION C 11/6/15
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