ATmega64L-8AU datasheet, PDF - EEWORLD Datasheet

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ATmega64L-8AU: DescriptionDevelopment Boards u0026 Kits - ARM; CategoryThe embedded processor and controller Microcontrollers and processors; File Size5MB，415 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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Development Boards u0026 Kits - ARM

ATmega64L-8AU Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	QFP
package instruction	TQFP-64
Contacts	64
Reach Compliance Code	unknown
ECCN code	EAR99
Factory Lead Time	1 week
core architecture	AVR
Device core	AVR
clock speed	16
Memory	4
flash memory	64
were able	0
Adc channel	8
ADC resolution	10
Samacsys Description	ATMEGA64L-8AU, 8 bit AVR Microcontroller 8MHz 2, 64kb Flash, 4kb RAM, I2C SPI 64-Pin TQFP
Has ADC	YES
Address bus width	16
bit size	8
CPU series	AVR RISC
maximum clock frequency	8 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
length	14 mm
Humidity sensitivity level	3
Number of I/O lines	53
Number of terminals	64
On-chip program ROM width	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TQFP
Encapsulate equivalent code	LCC64,.35SQ,20
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3/5 V
Certification status	Not Qualified
RAM (bytes)	4096
rom(word)	32768
ROM programmability	FLASH
Maximum seat height	1.2 mm
speed	8 MHz
Maximum slew rate	5 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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Features

•

High-performance, Low-power Atmel AVR

8-bit Microcontroller

•

Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers + Peripheral Control Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments

– 64 Kbytes of In-System Reprogrammable Flash program memory

– 2 Kbytes EEPROM

– 4 Kbytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Up to 64 Kbytes Optional External Memory Space

– Programming Lock for Software Security

– SPI Interface for In-System Programming

JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and

Capture Mode

– Real Time Counter with Separate Oscillator

– Two 8-bit PWM Channels

– 6 PWM Channels with Programmable Resolution from 1 to 16 Bits

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels

2 Differential Channels with Programmable Gain (1x, 10x, 200x)

– Byte-oriented Two-wire Serial Interface

– Dual Programmable Serial USARTs

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

– Software Selectable Clock Frequency

– ATmega103 Compatibility Mode Selected by a Fuse

– Global Pull-up Disable

I/O and Packages

– 53 Programmable I/O Lines

– 64-lead TQFP and 64-pad QFN/MLF

Operating Voltages

– 2.7V - 5.5V for Atmel ATmega64L

– 4.5V - 5.5V for Atmel ATmega64

Speed Grades

– 0 - 8 MHz for ATmega64L

– 0 - 16 MHz for ATmega64

•

8-bit Atmel

Microcontroller

with 64K Bytes

In-System

Programmable

Flash

ATmega64

ATmega64L

•

2490R–AVR–02/2013

ATmega64(L)

The ATmega64 provides the following features: 64 Kbytes of In-System Programmable Flash

with Read-While-Write capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O

lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Coun-

ters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an

8-channel, 10-bit ADC with optional differential input stage with programmable gain, program-

mable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant

JTAG test interface, also used for accessing the On-chip Debug system and programming, and

six software selectable power saving modes. The Idle mode stops the CPU while allowing the

SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down

mode saves the register contents but freezes the Oscillator, disabling all other chip functions

until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer contin-

ues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.

The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer

and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crys-

tal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast

start-up combined with low power consumption. In Extended Standby mode, both the main

Oscillator and the asynchronous timer continue to run.

The device is manufactured using Atmel’s high-density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-

gram running on the AVR core. The Boot Program can use any interface to download the

Application Program in the Application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the Atmel ATmega64 is a powerful microcontroller that provides a highly-flexible

and cost-effective solution to many embedded control applications.

The ATmega64 AVR is supported with a full suite of program and system development tools

including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators,

and evaluation kits.

ATmega103 and

ATmega64

Compatibility

The ATmega64 is a highly complex microcontroller where the number of I/O locations super-

sedes the 64 I/O location reserved in the AVR instruction set. To ensure backward compatibility

with the ATmega103, all I/O locations present in ATmega103 have the same location in

ATmega64. Most additional I/O locations are added in an Extended I/O space starting from 0x60

to 0xFF (that is, in the ATmega103 internal RAM space). These location can be reached by

using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions.

The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the

increased number of Interrupt Vectors might be a problem if the code uses absolute addresses.

To solve these problems, an ATmega103 compatibility mode can be selected by programming

the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the

internal RAM is located as in ATmega103. Also, the extended Interrupt Vectors are removed.

The ATmega64 is 100% pin compatible with ATmega103, and can replace the ATmega103 on

current printed circuit boards. The application notes “Replacing ATmega103 by ATmega128”

and “Migration between ATmega64 and ATmega128” describes what the user should be aware

of replacing the ATmega103 by an ATmega128 or ATmega64.

2490R–AVR–02/2013

ATmega64(L)

ATmega103

Compatibility Mode

By programming the M103C Fuse, the ATmega64 will be compatible with the ATmega103

regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new fea-

tures in ATmega64 are not available in this compatibility mode, these features are listed below:

•

One USART instead of two, asynchronous mode only. Only the eight least significant bits of

the Baud Rate Register is available.

One 16 bits Timer/Counter with two compare registers instead of two 16 bits Timer/Counters

with three compare registers.

Two-wire serial interface is not supported.

Port G serves alternate functions only (not a general I/O port).

Port F serves as digital input only in addition to analog input to the ADC.

Boot Loader capabilities is not supported.

It is not possible to adjust the frequency of the internal calibrated RC Oscillator.

The External Memory Interface can not release any Address pins for general I/O, neither

configure different wait states to different External Memory Address sections.

Only EXTRF and PORF exist in the MCUCSR Register.

No timed sequence is required for Watchdog Timeout change.

Only low-level external interrupts can be used on four of the eight External Interrupt sources.

Port C is output only.

USART has no FIFO buffer, so Data OverRun comes earlier.

The user must have set unused I/O bits to 0 in ATmega103 programs.

Pin Descriptions

VCC

GND

Port A (PA7..PA0)

Digital supply voltage.

Ground.

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the ATmega64 as listed on

page

73.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATmega64 as listed on

page

74.

2490R–AVR–02/2013

ATmega64L-8AU Related Products

	ATmega64L-8AU	ATmega64L-8MU	ATMEGA64L-8AUR	ATMEGA64L-8MUR	ATmega64-16AU	ATMEGA64L-8AI	ATMEGA64-16AUR
Description	Development Boards u0026 Kits - ARM	Multilayer Ceramic Capacitors MLCC - SMD/SMT 50volts 0.68uF 10% X7R AUTO	8-bit Microcontrollers - MCU AVR 64KB FLSH 2KB EE 4KB SRAM-8MHz, IND	8-bit Microcontrollers - MCU AVR 64KB FLSH 2KB EE 4KB SRAM-8MHz, IND	USB Interface IC USB to Serial UART Enhanced IC SSOP-28	8-bit Microcontrollers - MCU AVR 64K FLASH 2KB EE 4K SRAM ADC 3V	8-bit Microcontrollers - MCU AVR 64KB FLSH 2KB EE 4KB SRAM-16MHZ 5V
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	incompatible	conform to
Maker	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)
Parts packaging code	QFP	QFN	QFP	QFN	QFP	QFP	QFP
package instruction	TQFP-64	MLF-64	TQFP, LCC64,.35SQ,20	MLF-64	TQFP-64	14 X 14 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026AEB, TQFP-64	TQFP-64
Contacts	64	64	64	64	64	64	64
Reach Compliance Code	unknown	unknown	compliant	compliant	unknown	unknown	unknown
Has ADC	YES	YES	YES	YES	YES	YES	YES
Address bus width	16	16	16	16	16	16	16
bit size	8	8	8	8	8	8	8
CPU series	AVR RISC	AVR RISC	AVR RISC	AVR RISC	AVR RISC	AVR RISC	AVR RISC
maximum clock frequency	8 MHz	8 MHz	8 MHz	8 MHz	16 MHz	8 MHz	16 MHz
DAC channel	NO	NO	NO	NO	NO	NO	NO
DMA channel	NO	NO	NO	NO	NO	NO	NO
External data bus width	8	8	8	8	8	8	8
JESD-30 code	S-PQFP-G64	S-XQCC-N64	S-PQFP-G64	S-XQCC-N64	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64
JESD-609 code	e3	e3	e3	e3	e3	e0	e3
length	14 mm	9 mm	14 mm	9 mm	14 mm	14 mm	14 mm
Number of I/O lines	53	53	53	53	53	53	53
Number of terminals	64	64	64	64	64	64	64
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
PWM channel	YES	YES	YES	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	UNSPECIFIED	PLASTIC/EPOXY	UNSPECIFIED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TQFP	HVQCCN	TQFP	HVQCCN	TQFP	TQFP	TQFP
Encapsulate equivalent code	LCC64,.35SQ,20	LCC64,.35SQ,20	LCC64,.35SQ,20	LCC64,.35SQ,20	LCC64,.35SQ,20	TQFP64,.63SQ,32	LCC64,.35SQ,20
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	FLATPACK, THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	FLATPACK, THIN PROFILE	FLATPACK, THIN PROFILE	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260	260	260	260	240	260
power supply	3/5 V	3/5 V	3/5 V	3/5 V	5 V	3/5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
RAM (bytes)	4096	4096	4096	4096	4096	4096	4096
rom(word)	32768	32768	32768	32768	32768	32768	32768
ROM programmability	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
Maximum seat height	1.2 mm	1 mm	1.2 mm	1 mm	1.2 mm	1.2 mm	1.2 mm
speed	8 MHz	8 MHz	8 MHz	8 MHz	16 MHz	8 MHz	16 MHz
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	2.7 V	2.7 V	2.7 V	2.7 V	4.5 V	2.7 V	4.5 V
Nominal supply voltage	3 V	3 V	3 V	3 V	5 V	3 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	MATTE TIN	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)
Terminal form	GULL WING	NO LEAD	GULL WING	NO LEAD	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.5 mm	0.8 mm	0.5 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	40	40	40	40	40	30	40
width	14 mm	9 mm	14 mm	9 mm	14 mm	14 mm	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	-	Lead free
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	-	EAR99
Factory Lead Time	1 week	1 week	-	1 week	1 week	-	1 week
core architecture	AVR	AVR	AVR	AVR	AVR	-	AVR
Device core	AVR	AVR	AVR	AVR	AVR	-	AVR
clock speed	16	16	16	16	16	-	16
Memory	4	4	4	4	4	-	4
flash memory	64	64	64	64	64	-	64
Adc channel	8	8	8	8	8	-	8
ADC resolution	10	10	10	10	10	-	10
Humidity sensitivity level	3	1	3	-	3	3	3
On-chip program ROM width	16	16	16	16	16	-	16
Maximum slew rate	5 mA	5 mA	5 mA	5 mA	20 mA	-	20 mA

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