NB7L572
2.5V / 3.3V Differential 4:1
Mux Input to 1:2 LVPECL
Clock/Data Fanout /
Translator
Multi−Level Inputs w/ Internal Termination
The NB7L572 is a high performance differential 4:1 Clock/Data
input multiplexer and a 1:2 LVPECL Clock/Data fanout buffer. The
INx/INx inputs includes internal 50
W
termination resistors and will
accept differential LVPECL, CML, or LVDS logic levels. The
NB7L572 incorporates a pair of Select pins that will choose one of
four differential inputs and will produce two identical LVPECL output
copies of Clock or Data operating up to 7 GHz or 10 Gb/s,
respectively. As such, NB7L572 is ideal for SONET, GigE, Fiber
Channel, Backplane and other Clock/Data distribution applications.
The NB7L572 INx/INx inputs, outputs and core logic are powered
by a 2.5 V
$5%
V or 3.3 V
$10%
power supply. The two differential
LVPECL outputs will swing 750 mV when externally terminated with
a 50
W
resistor to V
CC
– 2 V, and are optimized for low skew and
minimal jitter.
The NB7L572 is offered in a low profile 5x5 mm 32-pin QFN
Pb-free package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB7L572 is a member of the GigaComm™ family of high
performance clock products.
Features
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MARKING
DIAGRAM*
32
1
32
1
NB7L
572
AWLYYWWG
QFN32
MN SUFFIX
CASE 488AM
A
WL
YY
WW
G
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
IN0
50W
V
T0
50W
IN0
V
REFAC0
IN1
50W
V
T1
50W
IN1
V
REFAC1
IN2
50W
V
T2
50W
IN2
V
REFAC2
IN3
50W
V
T3
50W
IN3
V
REFAC3
SEL0
SEL1
0
Q0
Q0
Q1
Q1
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Data Rate > 10.7 Gb/s Typical
Data Dependent Jitter < 15 ps
Maximum Input Clock Frequency > 7 GHz Typical
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:2 LVPECL Outputs, < 15 ps max
4:1 Multi−Level Mux Inputs, Accepts LVPECL, CML LVDS
150 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 750 mV Peak-to-Peak, Typical
Operating Range: V
CC
= 2.375 V to 3.6 V
Internal 50
W
Input Termination Resistors
V
REFAC
Reference Output
−40°C
to +85°C Ambient Operating Temperature
These are Pb−Free Devices
1
2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
June, 2012
−
Rev. 2
1
Publication Order Number:
NB7L572/D
NB7L572
VREFAC3
VREFAC2
VT3
VT2
IN3
IN3
IN2
IN2
Exposed Pad (EP)
32
31
30
29
28
27
26
25
IN0
VT0
VREFAC0
IN0
IN1
VT1
VREFAC1
IN1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
VCC
Q1
Q1
VCC
NC
SEL1
VCC
NB7L572
10
12
13
14
15
SEL0
GND
VCC
VCC
NC
Figure 1. Pinout Configuration
(Top View)
Table 1. INPUT SELECT FUNCTION TABLE
SEL1*
0
0
1
1
SEL0*
0
1
0
1
Clock / Data Input Selected
IN0 Input Selected
IN1 Input Selected
IN2 Input Selected
IN3 Input Selected
*Defaults HIGH when left open.
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2
VCC
Q0
Q0
16
11
9
NB7L572
Table 2. PIN DESCRIPTION
Pin
1, 4
5, 8
25, 28
29, 32
2, 6
26, 30
15
18
14, 19
10, 13, 16
17, 20, 23
11, 12
21, 22
9, 24
3
7
27
31
−
Name
IN0, IN0
IN1, IN1
IN2, IN2
IN3, IN3
VT0, VT1
VT2, VT3
SEL0
SEL1
NC
VCC
Q0, Q0
Q1, Q1
GND
VREFAC0
VREFAC1
VREFAC2
VREFAC3
EP
−
LVTTL/LVCMOS
Input
−
−
LVPECL Output
I/O
LVPECL, CML,
LVDS Input
Description
Non−inverted, Inverted, Differential Clock or Data Inputs.
Internal 100
W
Center−tapped Termination Pin for INx / INx
Input Select pins, default HIGH when left open through a 28k−W pull−up resistor. Input
logic threshold is V
CC
/2. See Select Function, Table 1.
No Connect
Positive Supply Voltage. All V
CC
pins must be connected to the positive power supply
for correct DC and AC operation.
Inverted, Non−inverted Differential Outputs.
Negative Supply Voltage, connected to Ground
Output Voltage Reference for Capacitor−Coupled Inputs
−
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be elec-
trically connected to GND.
1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or left
open, and if no signal is applied on INx / INx input, then the device will be susceptible to self−oscillation.
2. All VCC, and GND pins must be externally connected to a power supply for proper operation.
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3
NB7L572
Table 3. ATTRIBUTES
Characteristic
ESD Protection
Input Pullup Resistor (R
PU
)
Moisture Sensitivity (Note 3)
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
QFN32
Human Body Model
Machine Model
Value
> 4 kV
> 150 V
28 kW
Level 1
UL 94 V−0 @ 0.125 in
205
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
INPP
I
out
I
IN
T
A
T
stg
q
JA
q
JC
T
sol
Positive Power Supply
Positive Input Voltage
Differential Input Voltage |IN – IN|
LVPECL Output Current
Input Current Through RT (50
W
Resistor)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 4)
Thermal Resistance (Junction−to−Case) (Note 4)
Wave Solder
v
20 sec
0 lfpm
500 lfpm
QFN−32
QFN−32
QFN−32
Continuous
Surge
Parameter
Condition 1
GND = 0 V
GND = 0 V
Condition 2
Rating
−0.5
to +4.0
−0.5
to V
CC
+0.5
1.89
50
100
$40
−40
to +85
−65
to +150
31
27
12
265
Unit
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4
NB7L572
Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT
V
CC
= 2.375 V to 3.6 V, GND = 0 V, TA =
−40°C
to +85°C
(Note 6)
Symbol
POWER SUPPLY
V
CC
I
CC
V
OH
Power Supply Voltage
V
CC
= 2.5V
V
CC
= 3.3 V
2.375
3.0
2.5
3.3
90
2.625
3.6
110
V
mA
Characteristic
Min
Typ
Max
Unit
Power Supply Current for V
CC
(Inputs and Outputs Open)
Output HIGH Voltage (Note 6)
V
CC
– 1145
1355
2155
V
CC
– 2000
500
1300
LVPECL OUTPUTS
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
– 900
1600
2400
V
CC
– 1700
800
1600
V
CC
– 825
1675
2475
V
CC
– 1500
1000
1800
mV
V
OL
Output LOW Voltage (Note 6)
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED
(Figures 4 & 6) (Note 7)
V
IH
V
IL
V
th
V
ISE
VREFAC
V
REF−AC
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
R
TIN
Output Reference Voltage (100
mA
Load)
V
CC
– 1500
1200
0
100
800
−150
−150
V
CC
– 1200
V
CC
– 1000
V
CC
V
IHD
– 100
1200
V
CC
– 50
150
150
mV
Single−Ended Input HIGH Voltage
Single−Ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 8)
Single−Ended Input Voltage (V
IH
– V
IL
)
V
th
+ 100
GND
1100
200
V
CC
V
th
– 100
V
CC
– 100
2400
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 5 & 7) (Note 9)
Differential Input HIGH Voltage (IN, IN)
Differential Input LOW Voltage (IN, IN)
Differential Input Voltage (IN, IN) (V
IHD
– V
ILD
)
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 8)
Input HIGH Current IN/IN (VT IN/VT IN Open)
Input LOW Current IN/IN (VT IN/VT IN Open)
mV
mV
mV
mV
mA
mA
CONTROL INPUT
(SELx Pin)
Input HIGH Voltage for Control Pin
Input LOW Voltage for Control Pin
Input HIGH Current
Input LOW Current
−215
2.0
GND
V
CC
0.8
40
0
V
V
mA
mA
TERMINATION RESISTORS
Internal Input Termination Resistor (Measured from INx to VTx)
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and Output parameters vary 1:1 with V
CC
.
6. LVPECL outputs loaded with 50
W
to V
CC
−
2V for proper operation.
7. Vth, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
10. V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
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