CD-700-KAF-NBB-39.321 datasheet, PDF

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CD-700-KAF-NBB-39.321: DescriptionPLL/Frequency Synthesis Circuit, CQCC16; CategoryAnalog mixed-signal IC The signal circuit; File Size141KB，14 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

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CD-700-KAF-NBB-39.321 Overview

PLL/Frequency Synthesis Circuit, CQCC16

CD-700-KAF-NBB-39.321 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	QCCN, LCC16,.2X.3,40
Reach Compliance Code	compliant
JESD-30 code	R-XQCC-N16
JESD-609 code	e4
Humidity sensitivity level	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC
encapsulated code	QCCN
Encapsulate equivalent code	LCC16,.2X.3,40
Package shape	RECTANGULAR
Package form	CHIP CARRIER
power supply	5 V
Certification status	Not Qualified
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Gold (Au) - with Nickel (Ni) barrier
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	QUAD
Base Number Matches	1

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CD-700

Complete VCXO based Phase Lock Loop

Features

•

5 x 7.5 x 2 mm, smallest VCXO PLL available

•

Output Frequencies to 65.536MHz

•

5.0 or 3.3 Vdc operation

•

Tri-State Output

•

Loss of Signal Alarm

•

VCXO with CMOS outputs

•

0/70 or –40/85

°C

temperature range

•

Hermetically sealed ceramic SMD package

Applications

•

Frequency Translation

•

Clock Smoothing, Clock Switching

•

NRZ Clock recovery

LOS

(8)

PHO OPN

(3)

(2)

OPOUT

(1)

(16)

LOSIN

(4)

•

DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

•

Low jitter PLL’s

DATAIN

(5)

CLKIN

(6)

VCXO

Phase

Detector

and LOS

OP-Amp

Optional

2N Divider

OUT1

(13)

Description

OUT2

(11)

RCLK RDATA

(9)

(10)

OPP

(15)

GND

(7)

VDD

(14)

HIZ

(12)

The VI CD-700 is a user-configurable crystal

based PLL integrated circuit. It includes a digital

phase detector, op-amp, VCXO and additional

integrated functions for use in digital

synchronization applications. Loop filter software

is available as well SPICE models for circuit

simulation.

Figure 1, CD-700 block diagram

Vectron International 166 Glover Avenue, Norwalk CT 06856-5160

Tel:1-88-VECTRON-1

e-mail: vectron@vectron.com

CD-700, VCXO Based PLL

CD-700 Theory of Operation

Phase Detector

The phase detector has two buffered inputs, DATAIN and CLKIN, which are designed to switch at 1.4

volts. DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which

have about a 50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these

outputs. CLKIN and DATAIN and are protected by ESD diodes and should not exceed the power supply

voltage or ground by more than a few hundred millivolts.

The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to

produce a DC signal proportional to the phase between the CLKIN and DATAIN signals, see figure 4 for a

block diagram and figure 5 for a open loop transfer curve. This simplies the PLL design as the designer

does not have to filter narrow pulse signal to a DC level. Under locked conditions the rising edge CLKIN

will be centered in the middle of the DATAIN signal, see Figure 6.

The phase detector gain is 0.53V/rad x data density (for 5volt operation) and 0.35V/rad x data density for

3.3 volt operation. Data density = 1.0 for clock signals and is system dependent on coding and design for

NRZ signals, but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN frequencies greater than 1MHz but produces

significant ripple when inputs are less than 200kHz. Additional filtering is required for lower input

frequencies applications such as 8kHz, see Figures 8 and 9 as examples.

Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC gain,

so under normal locked conditions and input frequencies >1MHz, PHO will be about V

/2 and will not

vary signifigantly with changes in input frequency (within lock range). The control voltage (pin 16) will vary

according to the input frequency offset, but PHO will remain relatively constant.

Data In

(pin 5)

Clock In

(pin 6)

30 kΩ

20 kΩ

PHO

(pin 3)

Gain = V

/ 2π

Gain = 2 / 3

Figure 4, Simplified Phase Detector Block Diagram

Vectron International

•

166 Glover Avenue, Norwalk, CT 06856

•

Tel: 1-88-VECTRON-1• http://www.vectron.com

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