EMIF10-COM01C2
IPAD™
EMI Filter including ESD protection
Main product characteristics
EMI filtering and ESD protection for:
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Computers and printers
Communication systems
Mobile phones
Lead free coated Flip-Chip
(25 Bumps)
Description
The EMIF10-COM01C2 is a highly integrated
device designed to suppress EMI / RFI noise in all
systems subjected to electromagnetic
interferences. The EMIF10 Flip-Chip packaging
means the package size is equal to the die size.
Additionally, this filter includes an ESD protection
circuitry which prevents damage to the application
when subjected to ESD surges up to 15 kV.
Order code
Part Number
EMIF10-COM01C2
Marking
FE
Figure 1.
Pin configuration (Bump side)
5
I5
Benefits
■
■
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■
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4
I4
3
I3
2
I2
1
I1
EMI symmetrical (I/O) low-pass filter
Coating resin on flat side
Very low PCB space consuming: < 6 mm
2
Very thin package: 0.65 mm
High efficiency in ESD suppression on both
input and output pins
High reliability offered by monolithic integration
Lead free package
Figure 2.
Basic cell configuration
Low-pass Filter
GND
GND
GND
GND
GND
I10
I9
I8
I7
I6
A
B
C
D
E
010
09
08
07
06
05
04
03
02
01
Complies with the following standards:
IEC 61000-4-2 level 4
15 kV (air discharge)
8 kV (contact discharge)
Input
Output
TM: IPAD is a trademark of STMicroelctronics
R
I/O
= 200
Ω
C
line
= 45 pF
April 2006
Rev4
1/7
www.st.com
7
Characteristics
EMIF10-COM01C2
1
Characteristics
Table 1.
Symbol
V
PP
T
j
T
op
T
stg
Absolute Ratings
(T
amb
= 25 °C)
Parameter and test conditions
ESD discharge IEC61000-4-2, air discharge
ESD discharge IEC61000-4-2, contact discharge
Junction temperature
Operating temperature range
Storage temperature range
Value
15
8
125
- 40 to + 85
- 55 to + 150
Unit
kV
°C
°C
°C
Table 2.
Symbol
V
BR
I
RM
V
RM
V
CL
R
d
I
PP
R
I/O
C
line
Symbol
V
BR
I
RM
R
d
R
I/O
C
line
t
LH
Electrical Characteristics
(T
amb
= 25 °C)
Parameter
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Dynamic impedance
Peak pulse current
Resistance between Input and Output
Input capacitance per line
slope : 1 / R
d
I
PP
V
CL
V
BR
V
RM
I
RM
I
R
I
V
Test conditions
I
R
= 1 mA
V
RM
= 3 V per line
I
PP
= 10 A, t
p
= 2.5 µs
Min.
6
Typ.
8
Max.
10
500
Unit
V
nA
Ω
1
180
200
45
220
50
25
Ω
pF
ns
At 0 V bias
V
input
= 2.8 V
R
load
= 100 kΩ
2/7
EMIF10-COM01C2
Characteristics
Figure 3.
0.00
dB
-10.00
-20.00
S21(db) attenuation
measurement
(1)
Figure 4.
0.00
dB
-10.00
Analog crosstalk
-20.00
-30.00
-40.00
-50.00
-30.00
-40.00
-50.00
100.0k
1.0M
10.0M
100.0M
f/Hz
1.0G
-60.00
-70.00
-80.00
-90.00
-100.00
100.0k
1.0M
Xtalk 1/2 448
10.0M
f/Hz
100.0M
Xtalk 1/2 342
1.0G
1. Spikes at high frequencies are induced by the PCB layout
Figure 5.
ESD response to IEC 61000-4-2
Figure 6.
(+15 kV air discharge) on one input
(V
in
) and on one output (V
out
)
ESD response to IEC 61000-4-2
(-15 kV air discharge) on one input
(V
in
) and on one output (V
out
)
V(in1)
V(in1)
V(out1)
V(out1)
Figure 7.
Rise time measurement
EMIF10-COM01C2
In
Out
Vout
Square signal
Generator Vc = 2.8V
Vin
100k
Vout
Vin
3/7
Characteristics
EMIF10-COM01C2
Figure 8.
C(pF)
50
Capacitance versus reverse applied
voltage
F=1MHz
Vosc=30mV
40
30
20
10
0
1
2
VR(V)
3
4
5
Figure 9.
in
Aplac model
200R
out
MODEL = demif10
MODEL = demif10
Demif10 model
BV = 7
IBV = 1m
CJO = 25p
M = 0.3333
RS = 1
VJ = 0.6
TT = 100n
sub
1.1
PCB grounding recommendations
In order to ensure a good efficiency in terms of ESD protection and filtering behavior, we
recommend to implement microvias (100 µm dia.) between the GND bumps and the GND
layer. GND bumps can be connected together in PCB layer 1, and in addition, if possible,
use through hole vias (200 µm dia.) in both sides of filter to improve contact to GND (layer).
This layout will minimize the distance to the ground and thus parasitic inductances. In
addition, we recommend to have GND plane wherever possible.
4/7
EMIF10-COM01C2
Ordering Information Scheme
2
Ordering Information Scheme
EMIF
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
C = coated flip-chip
x = 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
yy
-
xxx zz
Cx
3
Package information
Figure 10. Flip-Chip package dimensions
500 µm ± 50
315 µm ± 50
500 µm ± 50
695 µm ± 70
2.42 mm ± 50 µm
Figure 11. Foot print recommendations Figure 12. Marking
2.42 mm ± 50 µm
Copper pad Diameter:
250 µm recommended, 300 µm max
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
E
Solder stencil opening: 330 µm
Solder mask opening recommendation:
340 µm min for 300 µm copper pad diameter
x x z
y ww
5/7
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