MC100LVEL11
3.3V ECL 1:2
Differential Fanout Buffer
Description
The MC100LVEL11 is a differential 1:2 fanout buffer. The device is
functionally similar to the E111 device but with higher performance
capabilities. Having within-device skews and output transition times
significantly improved over the E111, the LVEL11 is ideally suited for
those applications which require the ultimate in AC performance.
The differential inputs of the LVEL11 employ clamping circuitry to
maintain stability under open input conditions. If the inputs are left open
(pulled to V
EE
) the Q outputs will go LOW.
Features
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MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
KVL11
ALYW
G
1
•
•
•
•
•
•
•
•
•
330 ps Propagation Delay
5 ps Skew Between Outputs
High Bandwidth Output Transitions
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−3.0
V to
−3.8
V
Internal Input Pulldown Resistors on D,
Pullup and Pulldown Resistors on D
Q Output will Default LOW with Inputs Open or at V
EE
Pb−Free Packages are Available
8
KV11
ALYWG
G
1
1
DFN8
MN SUFFIX
CASE 506AA
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
Q
0
1
8
V
CC
Q
0
2
7
D
Q
1
3
6
D
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q
1
4
5
V
EE
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 1. Logic Diagram and Pinout Assignment
©
Semiconductor Components Industries, LLC, 2009
January, 2009
−
Rev. 11
1
Publication Order Number:
MC100LVEL11/D
3Z M
G
G
4
MC100LVEL11
Table 1. PIN DESCRIPTION
Pin
Q0, Q0; Q1, Q1
D, D
V
CC
V
EE
EP
ECL Data Outputs
ECL Data Inputs
Positive Supply
Function
Table 2. ATTRIBUTES
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charge Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
T
sol
q
JC
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Wave Solder
Pb
Pb−Free
0 lpfm
500 lpfm
Standard Board
0 lpfm
500 lpfm
Standard Board
0 lfpm
500 lfpm
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
(Note 2)
DFN8
SOIC−8
SOIC−8
SOIC−8
TSSOP−8
TSSOP−8
TSSOP−8
DFN8
DFN8
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
8 to 0
−8
to 0
6 to 0
−6
to 0
50
100
−40
to +85
−65
to +150
190
130
41 to 44
±
5%
185
140
41 to 44
±
5%
129
84
265
265
35 to 40
Units
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
°C/W
Thermal Resistance (Junction−to−Case)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁ
Á
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁ
Á
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁ
Á
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁ
Á
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁ
Á
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁ
Á
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁ
Á
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁÁÁÁÁ
Á
Negative Supply
(DFN8 only) Thermal exposed pad must be connected to
a sufficient thermal conduit. Electrically connect to the
most negative supply (GND) or leave unconnected, float-
ing open.
Characteristics
Value
75 kW
75 kW
> 4 KV
> 400 V
> 2 kV
Level 1
UL 94 V−0 @ 0.125 in
63
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2
MC100LVEL11
Table 4. LVPECL DC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0.0 V (Note 3)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
V
pp
< 500 mV
V
pp
y
500 mV
Input HIGH Current
Input LOW Current
D
D
0.5
−600
2215
1470
2135
1490
Min
Typ
24
2295
1605
Max
28
2420
1745
2420
1825
2275
1490
2135
1490
Min
25°C
Typ
24
2345
1595
Max
28
2420
1680
2420
1825
2275
1490
2135
1490
Min
85°C
Typ
25
2345
1595
Max
30
2420
1680
2420
1825
Unit
mA
mV
mV
mV
mV
1.2
1.4
3.1
3.1
150
1.1
1.3
3.1
3.1
150
1.1
1.3
3.1
3.1
150
V
V
mA
mA
mA
I
IH
I
IL
0.5
−600
0.5
−600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
4. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
5. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1.0 V.
Table 5. LVNECL DC CHARACTERISTICS
V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 6)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
V
pp
< 500 mV
V
pp
y
500 mV
Input HIGH Current
Input LOW Current
D
D
0.5
−600
−108
5
−183
0
−1165
−181
0
Min
Typ
24
−100
5
−169
5
Max
28
−880
−155
5
−880
−147
5
−102
5
−181
0
−1165
−181
0
Min
25°C
Typ
24
−955
−170
5
Max
28
−880
−162
0
−880
−147
5
−102
5
−181
0
−1165
−181
0
Min
85°C
Typ
25
−955
−170
5
Max
30
−880
−162
0
−880
−147
5
Unit
mA
mV
mV
mV
mV
−2.1
−1.9
−0.2
−0.2
150
−2.2
−2.0
−0.2
−0.2
150
−2.2
−2.0
−0.2
−0.2
150
V
V
mA
mA
mA
I
IH
I
IL
0.5
−600
0.5
−600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
7. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
8. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1.0 V.
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MC100LVEL11
Table 6. AC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 9)
−40°C
Symbol
f
max
t
PLH
t
PHL
t
SKEW
Characteristic
Maximum Toggle Frequency
Propagation Delay to Output
Within-Device Skew (Note 10)
Device−to−Device (Note 11)
Duty Cycle Skew (Note 12)
Random Clock Jitter (RMS)
Input Swing (Note 13)
Output Rise/Fall Times Q
(20%
−
80%)
200
120
1000
320
200
120
220
235
5
10
385
20
150
20
255
Min
Typ
Max
Min
25°C
Typ
1.0
330
5
10
0.6
1000
320
200
120
1000
320
405
20
150
20
285
5
10
435
20
150
20
Max
Min
85°C
Typ
Max
Unit
GHz
ps
ps
t
JITTER
V
PP
t
r
t
f
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. V
EE
can vary
±0.3
V.
10. Within-device skew defined as identical transitions on similar paths through a device.
11. Device−to−device skew for identical transitions at identical V
CC
levels.
12. Duty cycle skew is the difference between a t
PLH
and t
PHL
propagation delay through a device.
13. V
PP
(min) is the minimum input swing for which AC parameters guaranteed. The device will function properly with input swings below 200 mV,
however, AC delays may move outside of the specified range. The device has a DC gain of
≈40.
800
600
VOUT(PP)(mV)
400
200
0
0
200
400
600
800
1000
f (MHz)
1200
1400
1600
1800
2000
Figure 2. Output Swing versus Frequency
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MC100LVEL11
ORDERING INFORMATION
Device
MC100LVEL11D
MC100LVEL11DG
MC100LVEL11DR2
MC100LVEL11DR2G
MC100LVEL11DT
MC100LVEL11DTG
MC100LVEL11DTR2
MC100LVEL11DTR2G
MC100LVEL11MNR4
MC100LVEL11MNR4G
Package
SOIC−8
SOIC−8
(Pb−Free)
SOIC−8
SOIC−8
(Pb−Free)
TSSOP−8
TSSOP−8
(Pb−Free)
TSSOP−8
TSSOP−8
(Pb−Free)
DFN8
DFN8
(Pb−Free)
Shipping
†
98 Units / Rail
98 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
100 Units / Rail
100 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
1000 / Tape & Reel
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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