DATASHEET
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
Recommended Applications
2 Output synthesizer for PCIe Gen1/2/3 and Ethernet
5V41235
Features/Benefits
•
16-pin TSSOP and QFN packages; small board footprint
•
Spread-spectrum capable; reduces EMI
•
Outputs can be terminated to LVDS; can drive a wider
variety of devices
General Description
The 5V41235 is a PCIe Gen2/3 compliant spread spectrum
capable clock generator. The device has 2 differential
HCSL outputs and can be used in communication or
embedded systems to substantially reduce
electro-magnetic interference (EMI). The spread amount
and output frequency are selectable via select pins. The
5V41235 can also supply 25 MHz, 125 MHz and 200 MHz
outputs for applications such as Ethernet.
•
TSSOP package: 25MHz, 100MHz, 125MHz and
200MHz output frequencies.
•
QFN package: 100MHz and 200MHz output frequencies.
•
OE control pin; greater system power management
•
Spread% and frequency pin selection; no software
required to configure device
•
Industrial temperature range available; supports
Output Features
•
2 - 0.7V current mode differential HCSL output pairs
demanding embedded applications
Key Specifications
•
•
•
•
Cycle-to-cycle jitter < 100 ps
Output-to-output skew < 50 ps
PCIe Gen2 phase jitter < 3.0ps RMS
PCIe Gen3 phase jitter <1.0ps RMS
Block Diagram
VDD
2
SS1:SS0
2
CLK0
Control
Logic
Phase Lock Loop
CLK1
CLK1
CLK0
S1:S0
2
X1/ICLK
25 MHz
crystal or clock X2
Optional tuning crystal
capacitors
Clock
Buffer/
Crystal
Oscillator
2
GND
OE
Rr(IREF)
IDT®
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
1
5V41235
MAY 5, 2017
5V41235
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
Pin Assignments
VDDXD
S0
S1
SS0
X1/ICLK
X2
OE
GNDXD
SS1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
CLK0
CLK0
GNDODA
VDDODA
CLK1
CLK1
IREF
16 15 14 13
S1
SS0
X1/CLK
X2
1
2
3
4
CLK0
1
16
VDDXD
CLK0#
12
11
10
9
8
IREF
GNDODA
VDDODA
CLK1
CLK1#
S0
5
OE
5V41235
6
GNDXD
7
SS1
16-pin (173 mil) TSSOP
16-pin QFN
Output Select Table 1 (MHz) - TSSOP Only
S1
0
0
1
1
Output/Spread Select Table 3 - QFN Only
S1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S0
0
1
0
1
CLK(1:0), CLK(1:0)
25M
100M
125M
200M
S0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
100MHz
200MHz
100MHz
100MHz
200MHz
Spread%
-0.5
-0.5
No spread
-1
-1
Reserved
Spread Selection Table 2 - TSSOP Only
SS1
0
0
1
1
SS0
0
1
0
1
Spread%
No Spread
Down -0.5
Down -0.75
No Spread
Reserved
Reserved
100MHz
200MHz
-1.5
-1.5
Reserved
Reserved
Reserved
200MHz
No spread
Reserved
Reserved
IDT®
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
2
5V41235
MAY 5, 2017
5V41235
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
Pin Descriptions
QFN Pin
Number
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TSSOP
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
S0
S1
SS0
X1/ICLK
X2
OE
GNDXD
SS1
IREF
CLK1
CLK1
VDDODA
GNDODA
CLK0
CLK0
VDDXD
Pin
Type
Input
Input
Input
Input
Input
Power
Input
Pin Description
Select pin 0. See Table1. Internal pull-up resistor.
Select pin 1. See Table 1. Internal pull-up resistor.
Spread Select pin 0. See Table 2. Internal pull-up resistor.
Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
Output enable. Tri-states outputs and device is not shut down. Internal
pull-up resistor.
Connect to ground.
Spread Select pin 1. See Table 2. Internal pull-up resistor.
Output Crystal connection. Leave unconnected for clock input.
Output Precision resistor attached to this pin is connected to the internal current
reference.
Output HCSL complementary clock output 1.
Output HCSL true clock output 1.
Power
Power
Connect to voltage supply +3.3 V for output driver and analog circuits
Connect to ground.
Output HCSL complementary clock output 0.
Output HCSL true clock output 0.
Power
Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
IDT®
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
3
5V41235
MAY 5, 2017
5V41235
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
Applications Information
External Components
A minimum number of external components are required for
proper operation.
Output Structures
IREF
=2.3 mA
6*IREF
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected
between each VDD pin and the ground plane, as close to
the VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300 ppm
of error across temperature in order for the 5V41235 to meet
PCI Express specifications.
R
R
475
See Output Termination
Sections - Pages 3 ~ 5
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
C
L
= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 7) * 2
For example, for a crystal with a 8pF load cap, each external
crystal cap would be 2pF [(8-7)*2=2].
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50, then R
R
= 475
(1%), providing IREF of 2.32 mA. The output current (I
OH
) is
equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the 5V41235
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines
section.
The 5V41235 can also be configured for LVDS compatible
voltage levels. See the
LVDS Compatible Layout
Guidelines
section.
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the 5V41235.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
IDT®
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
4
5V41235
MAY 5, 2017
5V41235
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
Layout Guidelines
SRC Reference Clock
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50ohm trace
L2 length, route as non-coupled 50ohm trace
L3 length, route as non-coupled 50ohm trace
Rs
Rt
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
D imension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
2 min to 16 max
1.8 min to 14.4 max
inch
inch
1
1
0.25 to 14 max
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L1
Rs
L2
L4
L4'
L1'
Rs
HCSL Output Buffer
L2'
Rt
Rt
PCI Express
Down Device
REF_CLK Input
L3'
L3
Figure 2: PCI Express Connector Routing
L1
Rs
L2
L4
L4'
L1'
Rs
HCSL Output Buffer
L2'
Rt
Rt
PCI Express
Add-in Board
REF_CLK Input
L3'
L3
IDT®
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
5
5V41235
MAY 5, 2017
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