HCC/HCF40104B
HCC/HCF40194B
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
.
.
.
.
.
.
.
.
.
.
.
MEDIUM-SPEED OPERATION : f
CL
= 9MHz
(typ.) @ V
DD
= 10V
FULLY STATIC OPERATION
SYNCHRONOUS PARALLEL OR SERIAL
OPERATION
THREE-STATE OUTPUTS (HCC/HCF40104B)
ASYNCHRONOUS
MASTER
RESET
(HCC/HCF40194B)
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT AT 20V FOR HCC DE-
VICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N° 13A, ”STANDARD SPE-
CIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Plastic Chip Carrier )
ORDER CODES :
HCC401XXBF
HCF401XXBEY
HCF401XXBC1
DESCRIPTION
The
HCC40104B, HCC40194B,
(extended tem-
perature range) and the
HCC40104B, HCF40194B
(intermediate temperature range) are monolithic in-
tegrated circuits, available in 16-lead dual in-line
plastic or ceramic package and plastic micro pack-
age. The
HCC/HCF 40104B
is a universal shift reg-
ister featuring parallel inputs, parallel outputs, SHIFT
RIGHT and SHIFT LEFT serial inputs, and a high-im-
pedance third output state allowing the device to be
used in bus-organized systems. In the parallel-load
mode (S0 and S1 are high), data is loaded into the
associated flip-flop and appears at the output after
the positive transition of the CLOCK input. During
loading, serial data flow is inhibited. Shift-right and
shift-left are accomplished synchronously on the
positive clock edge with serial data entered at the
SHIFT RIGHT and SHIFT LEFT serial inputs, re-
spectively. Clearing the register is accomplished by
setting both mode controls low and clocking the reg-
ister. When the output enable input is low, all outputs
assume the high impedance state. The
HCC/HCF40194B
is a universal shift register featur-
ing parallel inputs, parallel outputs SHIFT RIGHT and
SHIFT LEFT serial inputs, and a direct overriding
clear input. In the parallel-load mode (S0 and S1 are
high), data is loaded into the associated flip-flop and
June 1989
PIN CONNECTIONS
40104B
40194B
1/12
HCC/HCF40104B/40194B
appears at the output after the positive transition of
the CLOCK input. During loading, serial data flow is
inhibited. Shift right and shift left are accomplished
synchronously on the positive clock edge with data
entered at the SHIFT RIGHT and SHIFT LEFT serial
FUNCTIONAL DIAGRAMS
40104B
40194B
inputs, respectively. Clocking of the register is in-
hibited when both mode control inputs are low. When
low, the RESET input resets all stages and forces all
outputs low. The
HCC/HCF40194B
is similar to in-
dustry types 340194 and MC40194.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
*
V
i
I
I
P
t o t
Parameter
Supply Voltage :
H CC
Types
H C F
Types
Input Voltage
DC Input Current (any one input)
Total Power Dissipation (per package)
Dissipation per Output Transistor
for T
o p
= Full Package-temperature Range
Operating Temperature :
H CC
Types
H C F
Types
Storage Temperature
Value
– 0.5 to + 20
– 0.5 to + 18
– 0.5 to V
DD
+ 0.5
±
10
200
100
– 55 to + 125
– 40 to + 85
– 65 to + 150
Unit
V
V
V
mA
mW
mW
°C
°C
°C
T
o p
T
stg
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device
reliability.
* All voltages values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
V
I
T
o p
Parameter
Supply Voltage :
HC C
Types
H C F
Types
Input Voltage
Operating Temperature :
H CC
Types
H C F
Types
Value
3 to 18
3 to 15
0 to V
DD
– 55 to + 125
– 40 to + 85
Unit
V
V
V
°C
°C
2/12
京公网安备 11010802033920号
EEWORLD
