Added Effect of Noise Reduction on Start-Up Time Section .. 16
12/2014—Rev. 0 to Rev. A
Changes to Figure 36 to Figure 41 ............................................... 12
Changes to Figure 44 ..................................................................... 14
9/2014—Revision 0: Initial Version
Rev. F | Page 2 of 24
Data Sheet
SPECIFICATIONS
ADP7118
V
IN
= V
OUT
+ 1 V or 2.7 V, whichever is greater, V
OUT
= 5 V, EN = V
IN
, I
OUT
= 10 mA, C
IN
= C
OUT
= 2.2 µF, C
SS
= 0 pF, T
A
= 25°C for typical
specifications, T
J
= −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
Symbol
V
IN
I
GND
Test Conditions/Comments
I
OUT
= 0 µA
I
OUT
= 10 mA
I
OUT
= 200 mA
EN = GND
EN = GND, V
IN
= 20 V
I
OUT
= 10 mA, T
J
= 25°C
100 μA < I
OUT
< 200 mA, V
IN
= (V
OUT
+ 1 V) to 20 V,
T
J
= −40°C to +85°C
100 μA < I
OUT
< 200 mA, V
IN
= (V
OUT
+ 1 V) to 20 V
V
IN
= (V
OUT
+ 1 V) to 20 V
I
OUT
= 100 μA to 200 mA
100 μA < I
OUT
< 200 mA V
IN
= (V
OUT
+ 1 V) to 20 V
I
OUT
= 10 mA
I
OUT
= 200 mA
V
OUT
= 5 V
SS = GND
–0.8
–1.2
–1.8
–0.015
0.002
10
30
200
380
1.15
360
150
15
2.69
2.2
230
2.7 V ≤ V
IN
≤ 20 V
EN
HIGH
EN
LOW
EN
HYS
I
EN-LKG
t
EN-DLY
OUT
NOISE
PSRR
1.15
1.06
EN = V
IN
or GND
From EN rising from 0 V to V
IN
to 0.1 × V
OUT
10 Hz to 100 kHz, all output voltage options
1 MHz, V
IN
= 7 V, V
OUT
= 5 V
100 kHz, V
IN
= 7 V, V
OUT
= 5 V
10 kHz, V
IN
= 7 V, V
OUT
= 5 V
1.22
1.12
100
0.04
80
11
50
68
88
1.30
1.18
1
V
V
mV
µA
μs
µV rms
dB
dB
dB
Min
2.7
Typ
50
80
180
1.8
3.0
Max
20
140
190
320
10
+0.8
+1.5
+1.8
+0.015
0.004
1000
60
420
Unit
V
µA
µA
µA
µA
µA
%
%
%
%/V
%/mA
nA
mV
mV
µs
µA
mA
°C
°C
V
V
mV
SHUTDOWN CURRENT
OUTPUT VOLTAGE ACCURACY
Output Voltage Accuracy
I
GND-SD
V
OUT
LINE REGULATION
LOAD REGULATION
1
SENSE INPUT BIAS CURRENT
DROPOUT VOLTAGE
2
START-UP TIME
3
SOFT START SOURCE CURRENT
CURRENT-LIMIT THRESHOLD
4
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
UNDERVOLTAGE THRESHOLDS
Input Voltage Rising
Input Voltage Falling
Hysteresis
PRECISION EN INPUT
Logic High
Logic Low
Logic Hysteresis
Leakage Current
Delay Time
OUTPUT NOISE
POWER SUPPLY REJECTION RATIO
∆V
OUT
/∆V
IN
∆V
OUT
/∆I
OUT
SENSE
I-BIAS
V
DROPOUT
t
START-UP
SS
I-SOURCE
I
LIMIT
TS
SD
TS
SD-HYS
UVLO
RISE
UVLO
FALL
UVLO
HYS
250
T
J
rising
460
Based on an endpoint calculation using 100 μA and 200 mA loads. See Figure 7 for typical load regulation performance for loads less than 1 mA.
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output
voltages above 2.7 V.
3
Start-up time is defined as the time between the rising edge of EN to OUT being at 90% of the nominal value.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V or 4.5 V.
1
2
Rev. F | Page 3 of 24
ADP7118
INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
INPUT AND OUTPUT CAPACITANCE
Minimum Capacitance
1
Capacitor Effective Series Resistance (ESR)
1
Data Sheet
Symbol
C
MIN
R
ESR
Test Conditions/Comments
T
A
= −40°C to +125°C
T
A
= −40°C to +125°C
Min
1.5
0.001
Typ
Max
Unit
µF
Ω
0.3
The minimum input and output capacitance must be greater than 1.5 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
while Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. F | Page 4 of 24
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
SENSE/ADJ to GND
SS to GND
Storage Temperature Range
Junction Temperature (T
J
)
Operating Ambient Temperature (T
A
)
Range
Soldering Conditions
Rating
–0.3 V to +24 V
–0.3 V to VIN
–0.3 V to +24 V
–0.3 V to +6 V
–0.3 V to VIN or
+6 V (whichever is
less)
–65°C to +150°C
150°C
–40°C to +125°C
JEDEC J-STD-020
ADP7118
θ
JA
of the package is based on modeling and calculation using a
4-layer board. The θ
JA
is highly dependent on the application
and board layout. In applications where high maximum power
dissipation exists, close attention to thermal board design is
required. The value of θ
JA
may vary, depending on PCB material,
layout, and environmental conditions. The specified values of θ
JA
are based on a 4-layer, 4 inches × 3 inches circuit board. See
JESD51-7 and JESD51-9 for detailed information on the board
construction.
Ψ
JB
is the junction-to-board thermal characterization parameter
with units of °C/W. The Ψ
JB
of the package is based on
modeling and calculation using a 4-layer board. The JESD51-12,
Guidelines for Reporting and Using Electronic Package Thermal
Information,
states that thermal characterization parameters are
not the same as thermal resistances. Ψ
JB
measures the component
power flowing through multiple thermal paths rather than a
single path as in thermal resistance (θ
JB
). Therefore, Ψ
JB
thermal
paths include convection from the top of the package as well as
radiation from the package, factors that make Ψ
JB
more useful
in real-world applications. Maximum T
J
is calculated from the
board temperature (T
B
) and P
D
using the formula
T
J
=
T
B
+ (P
D
×
Ψ
JB
)
See JESD51-8 and JESD51-12 for more detailed information
about Ψ
JB
.
(2)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The
ADP7118
can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T
J
is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature of the device is dependent on the ambient
temperature, the power dissipation (P
D
) of the device, and the
junction-to-ambient thermal resistance of the package (θ
JA
).
Maximum T
J
is calculated from the T
A
and P
D
using the
formula
T
J
=
T
A
+ (P
D
×
θ
JA
)
(1)
THERMAL RESISTANCE
θ
JA
, θ
JC
, and Ψ
JB
are specified for the worst-case conditions, that
is, a device soldered in a circuit board for surface-mount packages.
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