P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core,
4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs
Rev. 5.1 — 20 August 2012
Product data sheet
1. General description
The P89LPC9331/9341/9351/9361 is a single-chip microcontroller, available in low cost
packages, based on a high performance processor architecture that executes instructions
in two to four clocks, six times the rate of standard 80C51 devices. Many system-level
functions have been incorporated into the P89LPC9331/9341/9351/9361 in order to
reduce component count, board space, and system cost.
2. Features and benefits
2.1 Principal features
4 kB/8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and
64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data
storage.
256-byte RAM data memory. P89LPC9351 and P89LPC9361 also include a 512-byte
auxiliary on-chip RAM.
512-byte customer data EEPROM on-chip allows serialization of devices, storage of
setup parameters, etc. (P89LPC9351/9361)
Dual 4-input multiplexed 8-bit ADC/DAC outputs. Two analog comparators with
selectable inputs and reference source.
Dual Programmable Gain Amplifiers (PGA) with selectable gains of 2x, 4x, 8x, or 16x
can be applied to ADCs and analog comparator inputs. (P89LPC9351/9361)
On-chip temperature sensor integrated with ADC module.
Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output).
A 23-bit system timer that can also be used as a real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I
2
C-bus
communication port and SPI communication port.
Capture/Compare Unit (CCU) provides PWM, input capture, and output compare
functions. (P89LPC9351/9361)
2.4 V to 3.6 V V
DD
operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
Enhanced low voltage (brownout) detect allows a graceful system shutdown when
power fails.
28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins
while using on-chip oscillator and reset options.
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
2.2 Additional features
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
Serial flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
Serial flash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
In-Application Programming (IAP) of the flash code memory. This allows changing the
code in a running application.
Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to
5
%,
requiring no external components. The watchdog prescaler is selectable from
eight values.
High-accuracy internal RC oscillator option, with clock doubler option, allows operation
without external oscillator components. The RC oscillator option is selectable and fine
tunable.
Clock switching on the fly among internal RC oscillator, watchdog oscillator, external
clock source provides optimal support of minimal power active mode with fast
switching to maximum performance.
Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1
A
(total power-down with voltage comparators disabled).
Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A software reset function is also available.
Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6,
P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is
specified for the entire chip.
Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
Only power and ground connections are required to operate the
P89LPC9331/9341/9351/9361 when internal reset option is selected.
Four interrupt priority levels.
Eight keypad interrupt inputs, plus two additional external interrupt inputs.
Schmitt trigger port inputs.
Second data pointer.
Emulation support.
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
2 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
3. Ordering information
Table 1.
Ordering information
Package
Name
P89LPC9331FDH
P89LPC9331HDH
P89LPC9341FDH
P89LPC9351FA
P89LPC9351FDH
P89LPC9361FDH
TSSOP28
TSSOP28
TSSOP28
PLCC28
TSSOP28
TSSOP28
Description
plastic thin shrink small outline package; 28
leads; body width 4.4 mm
plastic thin shrink small outline package; 28
leads; body width 4.4 mm
plastic thin shrink small outline package; 28
leads; body width 4.4 mm
plastic leaded chip carrier; 28 leads
plastic thin shrink small outline package; 28
leads; body width 4.4 mm
plastic thin shrink small outline package; 28
leads; body width 4.4 mm
Version
SOT361-1
SOT361-1
SOT361-1
SOT261-2
SOT361-1
SOT361-1
Type number
3.1 Ordering options
Table 2.
Ordering options
Flash memory
4 kB
4 kB
8 kB
8 kB
8 kB
16 kB
Temperature range
40 C
to +85
C
40 C
to +125
C
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
Frequency
0 MHz to 18 MHz
0 MHz to 18 MHz
0 MHz to 18 MHz
0 MHz to 18 MHz
0 MHz to 18 MHz
0 MHz to 18 MHz
Type number
P89LPC9331FDH
P89LPC9331HDH
P89LPC9341FDH
P89LPC9351FA
P89LPC9351FDH
P89LPC9361FDH
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
3 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
4. Block diagram
P89LPC9331/9341/9351/9361
ACCELERATED 2-CLOCK 80C51 CPU
4 kB/8 kB/16 kB
CODE FLASH
256-BYTE
DATA RAM
512-BYTE
AUXILIARY RAM
(1)
UART
internal bus
I
2
C-BUS
TXD
RXD
SCL
SDA
SPICLK
MOSI
MISO
SS
SPI
512-BYTE
DATA EEPROM
(1)
PORT 3
CONFIGURABLE I/Os
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
REAL-TIME CLOCK/
SYSTEM TIMER
TIMER 0
TIMER 1
T0
T1
CMP2
CIN2B
CIN2A
CMP1
CIN1A
CIN1B
OCA
OCB
OCC
OCD
ICA
ICB
AD10
AD11
AD12
AD13
DAC1
AD00
AD01
AD02
AD03
DAC0
P3[1:0]
P2[7:0]
ANALOG
COMPARATORS
P1[7:0]
P0[7:0]
CCU (CAPTURE/
COMPARE UNIT)
(1)
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
ADC1/DAC1
(2)
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
clock
ADC0/TEMP
SENSOR/DAC0
(3)
XTAL1
CRYSTAL
OR
RESONATOR XTAL2
CONFIGURABLE
OSCILLATOR
ON-CHIP RC
OSCILLATOR
WITH CLOCK
DOUBLER
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aad555
(1) P89LPC9351/9361
(2) PGA1 on P89LPC9351/9361
(3) PGA0 on P89LPC9351/9361
Fig 1.
Block diagram
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
4 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
5. Functional diagram
V
DD
V
SS
DAC1
AD01
AD10
AD11
AD12
AD13
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CLKOUT
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
XTAL2
PORT 0
PORT 1
TXD
RXD
T0
INT0
INT1
RST
AD00
AD03
AD02
MOSI
MISO
SS
SPICLK
SCL
SDA
P89LPC9331/
P89LPC9341
PORT 3
DAC0
XTAL1
PORT 2
002aae461
Fig 2.
Functional diagram (P89LPC9331/9341)
V
DD
V
SS
DAC1
AD01
AD10
AD11
AD12
AD13
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CLKOUT
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
XTAL2
PORT 0
PORT 1
P89LPC9351/
P89LPC9361
PORT 3
TXD
RXD
T0
INT0
INT1
RST
OCB
OCC
ICB
OCD
MOSI
MISO
SS
SPICLK
OCA
ICA
SCL
SDA
AD00
AD03
AD02
DAC0
XTAL1
PORT 2
002aad556
Fig 3.
Functional diagram (P89LPC9351/9361)
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
5 of 94
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