INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4011UB
gates
Quadruple 2-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Quadruple 2-input NAND gate
DESCRIPTION
The HEF4011UB is a quadruple 2-input NAND gate. This
unbuffered single stage version provides a direct
implementation of the NAND function. The output
impedance and output transition time depends on the input
voltage and input rise and fall times applied.
HEF4011UB
gates
Fig.2 Pinning diagram.
HEF4011UBP(N):
Fig.1 Functional diagram.
HEF4011UBD(F):
HEF4011UBT(D):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3
Schematic diagram (one gate). The
splitting-up of the n-transistors provide
identical inputs.
FAMILY DATA, I
DD
LIMITS category GATES
See Family Specifications for V
IH
/V
IL
unbuffered stages
January 1995
2
Philips Semiconductors
Product specification
Quadruple 2-input NAND gate
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
I
n
→
O
n
HIGH to LOW
5
10
15
5
LOW to HIGH
Output transition
times
HIGH to LOW
LOW to HIGH
Input capacitance
10
15
5
10
15
5
10
15
C
IN
t
TLH
t
THL
t
PLH
t
PHL
60
25
20
35
20
17
75
30
20
60
30
20
120
50
40
70
40
35
150
60
40
110
60
40
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
SYMBOL
TYP.
MAX.
HEF4011UB
gates
TYPICAL EXTRAPOLATION
FORMULA
25 ns
+
(0,70 ns/pF) C
L
12 ns
+
(0,27 ns/pF) C
L
10 ns
+
(0,20 ns/pF) C
L
8 ns
+
(0,55 ns/pF) C
L
9 ns
+
(0,23 ns/pF) C
L
9 ns
+
(0,16 ns/pF) C
L
15 ns
+
(1,20 ns/pF) C
L
6 ns
+
(0,48 ns/pF) C
L
4 ns
+
(0,32 ns/pF) C
L
10 ns
+
(1,00 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
500 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
5 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
25 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
3
Philips Semiconductors
Product specification
Quadruple 2-input NAND gate
HEF4011UB
gates
Fig.4
Typical transfer characteristics; one input, the other
input connected to V
DD
;
V
O
;
− − −
I
D
(drain current);
I
O
= 0; V
DD
= 5 V.
Fig.5
Typical transfer characteristics; one input, the other
input connected to V
DD
;
V
O
;
− − −
I
D
(drain current);
I
O
= 0; V
DD
= 10 V.
Fig.6
Typical transfer characteristics; one input, the other
input connected to V
DD
;
V
O
;
− − −
I
D
(drain current);
I
O
= 0; V
DD
= 15 V.
January 1995
4
Philips Semiconductors
Product specification
Quadruple 2-input NAND gate
HEF4011UB
gates
Fig.7 Test set-up for measuring forward transconductance g
fs
= di
o
/dv
i
at v
o
is constant (see also graph Fig.8).
A : average,
B : average
+
2 s,
C : average
−
2 s, where ‘s’ is the observed standard deviation.
Fig.8 Typical forward transconductance g
fs
as a function of the supply voltage at T
amb
= 25
°C.
January 1995
5
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