F611AK393J630R datasheet, PDF - EEWORLD Datasheet

F611AK393J630R: DescriptionFilm Capacitors 630V 39000pF 5%; CategoryPassive components; File Size3MB，35 Pages; ManufacturerKEMET; Websitehttp://www.kemet.com

Download Datasheet Parametric View All

F611AK393J630R Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	F611AK393J630R	-	-	View	Buy Now

Film Capacitors 630V 39000pF 5%

Parameter Name	Attribute value
Product Category	Film Capacitors
Manufacturer	KEMET
RoHS	Details
Termination Style	Radial
Product	General Film Capacitors
Dielectric	Polyester
Capacitance	0.039 uF
Voltage Rating AC	220 VAC
Voltage Rating DC	0 VDC
Tolerance	5 %
Lead Spacing	10 mm
Lead Style	Straight
Minimum Operating Temperature	- 55 C
Maximum Operating Temperature	+ 105 C
Length	13 mm
Width	11 mm
Height	5 mm
Packaging	Ammo Pack
Capacitance - nF	39 nF
Capacitance - pF	39000 pF
Lead Diameter	0.6 mm
Factory Pack Quantity	800
Type	Metallized Polyester Film Capacitors

[Rawpixel RVB2601 development board trial experience] 4. General hardware timer test: 4. General Hardware Timer TestWhen using an operating system, if some tasks are performed in a software dead-wait manner, the system efficiency will inevitably be affected. Therefore, some slow period...; gs001588 XuanTie RISC-V Activity Zone

Ask a question about Verilog: I am a FPGA newbie, and now I have a Verilog question I would like to ask For example, there is an input data input [16:0] REG For ease of use, I now want to disassemble REG, such as a = REG[16:8]; b ...; littleshrimp FPGA/CPLD

Share MODBUS examples based on MSP430: This is the source code of the original author of tsg9456 in actual application, I hope it can help everyoneRun codeCopy code#include "synth.h"//-------------------------------------------------------...; 火辣西米秀 Microcontroller MCU

Using FPGA to collect images and store them in SD card: I am currently working on using a camera to continuously capture several images in FPGA, storing the images in SDRAM, and want to store them in a SD card in bmp format. I don't know NIOS design, so I ...; 微娴轩 EE_FPGA Learning Park

ATSAMD21, use ATMEL START to configure the internal DFLL48M CLOSE LOOP MODE to run at 48MHz: [b][color=#5E7384]This content is originally created by EEWORLD forum user [size=3]zhengwenbang[/size]. If you need to reprint or use it for commercial purposes, you must obtain the author's consent a...; zhengwenbang Microchip MCU

EEWORLD University ---- VLSI CADI - Theory: VLSI CADI-Theory : https://training.eeworld.com.cn/course/6101A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc.? How do we design these complex chips?? Answer: CAD s...; 木犯001号 Embedded System

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components