Changes to Figure 10 and Figure 13............................................. 10
Changes to Figure 14 and Figure 19............................................. 11
Changes to Figure 20 and Figure 25............................................. 12
Changes to Figure 32 ...................................................................... 14
Changes to Table 9 .......................................................................... 18
Changes to Readback Operation Section .................................... 20
Changes to Hardware Reset (RESET) Section ............................ 22
1/2016—Rev. 0 to Rev. A
Change to Table 14 ......................................................................... 21
2/2013—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
SPECIFICATIONS
AD5689/AD5687
V
DD
= 2.7 V to 5.5 V; 1.62 V ≤ V
LOGIC
≤ 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted. R
L
= 2 kΩ; C
L
= 200 pF.
Table 2.
Parameter
STATIC PERFORMANCE
1
AD5689
Resolution
Relative Accuracy
Differential Nonlinearity
AD5687
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error
Offset Error Drift
2
Gain Temperature Coefficient
2
DC Power Supply Rejection Ratio
2
DC Crosstalk
2
Min
Typ
Max
Unit
Test Conditions/Comments
16
±1
±1
±2
±3
±1
Bits
LSB
LSB
Bits
LSB
LSB
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
ppm
mV/V
µV
µV/mA
µV
Gain = 2
Gain = 1
Guaranteed monotonic by design
12
±0.12
0.4
+0.1
+0.01
±0.02
±0.01
±1
±1
0.15
±2
±3
±2
±1
±1
1.5
±1.5
±0.1
±0.1
±0.1
±0.2
Guaranteed monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
Gain = 2; TSSOP
Gain = 1; TSSOP
Of FSR/°C
DAC code = midscale, V
DD
= 5 V ± 10%
Due to single-channel, full-scale output change
Due to load current change
Due to powering down (per channel)
Gain = 1
Gain = 2; see Figure 24
R
L
= ∞
R
L
= 1 kΩ
5 V ± 10%, DAC code = midscale;
−30 mA ≤ I
OUT
≤ 30 mA
3 V ± 10%, DAC code = midscale;
−20 mA ≤ I
OUT
≤ 20 mA
See Figure 23
Coming out of power-down mode; V
DD
= 5 V
V
REF
= V
DD
= V
LOGIC
=5.5 V, gain = 1
V
REF
= V
DD
= V
LOGIC
=5.5 V, gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Per pin
OUTPUT CHARACTERISTICS
2
Output Voltage Range
Capacitive Load Stability
Resistive Load
3
Load Regulation
0
0
2
10
1
80
80
V
REF
2 × V
REF
V
V
nF
nF
kΩ
µV/mA
µV/mA
mA
Ω
µs
µA
µA
V
V
kΩ
kΩ
µA
V
V
pF
Short-Circuit Current
4
Load Impedance at Rails
5
Power-Up Time
REFERENCE INPUT
Reference Current
6
Reference Input Range
Reference Input Impedance
LOGIC INPUTS
2
Input Current
Input Low Voltage (V
INL
)
Input High Voltage (V
INH
)
Pin Capacitance
1
1
40
25
2.5
90
180
V
DD
V
DD
/2
16
32
±2
0.3 × V
LOGIC
0.7 × V
LOGIC
2
Rev. B | Page 3 of 24
AD5689/AD5687
Parameter
LOGIC OUTPUTS (SDO)
2
Output Low Voltage (V
OL
)
Output High Voltage (V
OH
)
Floating State Output Capacitance
POWER REQUIREMENTS
V
LOGIC
I
LOGIC
V
DD
V
DD
I
DD
Normal Mode
7
All Power-Down Modes
8
1
Data Sheet
Min
Typ
Max
0.4
V
LOGIC
− 0.4
4
1.62
2.7
V
REF
+ 1.5
0.59
1
5.5
3
5.5
5.5
0.7
4
6
Unit
V
V
pF
V
µA
V
V
mA
µA
µA
Test Conditions/Comments
I
SINK
= 200 μA
I
SOURCE
= 200 μA
Gain = 1
Gain = 2
V
IH
= V
DD
, V
IL
= GND, V
DD
= 2.7 V to 5.5 V
−40°C to +85°C
−40°C to +105°C
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV; it exists only when V
REF
= V
DD
with gain = 1 or when V
REF
/2 =
V
DD
with gain = 2. Linearity is calculated using a reduced code range of 256 to 65,280 (AD5689) and 12 to 4080 (AD5687).
2
Guaranteed by design and characterization; not production tested.
3
Channel A can have an output current of up to 30 mA. Similarly, Channel B can have an output current of up to 30 mA, up to a junction temperature of 110°C.
4
V
DD
= 5 V. The devices include current limiting that is intended to protect them during temporary overload conditions. Junction temperature may be exceeded during
current limit, but operation above the specified maximum operation junction temperature can impair device reliability.
5
When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 23).
6
Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift.
7
Interface inactive. Both DACs active. DAC outputs unloaded.
8
Both DACs powered down.
AC CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; 1.62 V ≤ V
LOGIC
≤ 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise
noted. Temperature range = −40°C to +105°C, typical at 25°C. Guaranteed by design and characterization, not production tested.
Table 3.
Parameter
1
Output Voltage Settling Time
AD5689
AD5687
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion (THD)
2
Output Noise Spectral Density (NSD)
Output Noise
Signal-to-Noise Ratio (SNR)
Spurious Free Dynamic Range (SFDR)
Signal-to-Noise-and-Distortion Ratio
(SINAD)
1
2
Min
Typ
5
5
0.8
0.5
0.13
0.1
0.2
0.3
−80
300
6
90
83
80
Max
8
7
Unit
µs
µs
V/µs
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
dB
dB
Test Conditions/Comments
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
1 LSB change around major carry
At ambient, BW = 20 kHz, V
DD
= 5 V, f
OUT
= 1 kHz
DAC code = midscale, 10 kHz, gain = 2
0.1 Hz to 10 Hz
At ambient, BW = 20 kHz, V
DD
= 5 V, f
OUT
= 1 kHz
At ambient, BW = 20 kHz, V
DD
= 5 V, f
OUT
= 1 kHz
At ambient, BW = 20 kHz, V
DD
= 5 V, f
OUT
= 1 kHz
See the Terminology section.
Digitally generated sine wave at 1 kHz.
Rev. B | Page 4 of 24
Data Sheet
TIMING CHARACTERISTICS
AD5689/AD5687
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 2.
V
DD
= 2.7 V to 5.5 V, 1.62 V ≤ V
LOGIC
≤ 5.5 V; V
REF
= 2.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter
1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates)
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SYNC Rising Edge to LDAC Rising Edge
SYNC Rising Edge to LDAC Falling Edge
LDAC Falling Edge to SYNC Rising Edge
Minimum Pulse Width Low
Pulse Activation Time
Power-Up Time
2
E
E
E
E
E
E
E
E
E
E
E
E
E
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
1.62 V ≤ V
LOGIC
< 2.7 V
Min
Max
20
10
10
15
5
5
10
20
870
16
15
20
30
840
30
30
4.5
2.7 V ≤ V
LOGIC
≤ 5.5 V
Min
Max
20
10
10
10
5
5
10
20
830
10
15
20
30
800
30
30
4.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
1
2
Guaranteed by design and characterization; not production tested.
Time to exit power-down to normal mode of operation, SYNC rising edge to 90% of DAC midscale value, with output unloaded.
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