STM32F303VDH6 datasheet, PDF - EEWORLD Datasheet

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STM32F303VDH6: DescriptionARM Microcontrollers - MCU Analog and DSP with FPU ARM Cortex-M4 MCU with 512 Kbytes Flash, 72 MHz CPU, MPU, CCM, 12-bit ADC 5 MSPS, PGA, comparators; Categorysemiconductor The embedded processor and controller; File Size11MB，1141 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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ARM Microcontrollers - MCU Analog and DSP with FPU ARM Cortex-M4 MCU with 512 Kbytes Flash, 72 MHz CPU, MPU, CCM, 12-bit ADC 5 MSPS, PGA, comparators

STM32F303VDH6 Parametric

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Product Category	ARM Microcontrollers - MCU
Manufacturer	STMicroelectronics
Factory Pack Quantity	2496

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RM0316

Reference manual

STM32F303xB/C/D/E, STM32F303x6/8, STM32F328x8,

STM32F358xC, STM32F398xE advanced ARM

-based MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32F303xB/C/D/E, STM32F303x6/x8, STM32F328x8, STM32F358xC

and STM32F398xE microcontroller memory and peripherals. The STM32F303xB/C/D/E,

STM32F303x6/x8, STM32F328x8, STM32F358xC and STM32F398xE devices will be

referred to as STM32F3xx throughout the document, unless otherwise specified.

The STM32F3xx is a family of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

relevant datasheets.

For information on the ARM C

ORTEX

-M4 core with FPU, please refer to the

STM32F3xx/STM32F4xx

programming manual (PM0214).

Related documents

•

STM32F303xB/C, STM32F303xD/E, STM32F303x6/8, STM32F328x8, STM32F358xC

and STM32F398xE datasheets available from the company website at

www.st.com.

•

STM32F3xx/F4xx Cortex -M4 programming manual (PM0214) available from the

company website at

www.st.com.

January 2017

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www.st.com

Contents

RM0316

Contents

Overview of the manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.1

2.2

2.3

List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.1

System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.1.1

3.1.2

3.1.3

3.1.4

3.1.5

S0: I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

S1: D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

S2: S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

S3, S4: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 51

Parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

CCM SRAM write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.2

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.2.1

3.2.2

3.3

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.3.1

3.3.2

3.4

3.5

Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.5.1

Embedded boot loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.1

4.2

Flash main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Flash memory functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.2.1

4.2.2

4.2.3

Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.3

Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.3.1

4.3.2

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Option byte block write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.4

4.5

Flash interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Flash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.5.1

4.5.2

4.5.3

4.5.4

4.5.5

4.5.6

4.5.7

4.5.8

Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . 78

Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 79

Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Flash address register (FLASH_AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Option byte register (FLASH_OBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Write protection register (FLASH_WRPR) . . . . . . . . . . . . . . . . . . . . . . . 83

4.6

Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . 88

6.1

6.2

6.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.3.1

6.3.2

6.3.3

CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 91

Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.4

CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

6.4.6

Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.1

Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.1.1

7.1.2

7.1.3

Independent A/D and D/A converter supply and reference voltage . . . . 96

Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

7.2

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

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7.2.1

7.2.2

7.2.3

RM0316

Power on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 97

Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 99

External NPOR signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.3

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . 108

PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.4

Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

7.4.1

7.4.2

7.4.3

Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

8.1

8.2

8.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

8.3.7

8.3.8

8.3.9

8.3.10

8.3.11

8.3.12

8.3.13

8.3.14

8.3.15

8.3.16

8.3.17

8.3.18

DMA interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

From ADC to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

From ADC to TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

From TIM and EXTI to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

From OPAMP to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

From TS to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

From VBAT to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

From VREFINT to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

From COMP to TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

From TIM to COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

From DAC to COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

From VREFINT to COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

From DAC to OPAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

From TIM to OPAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

From TIM to TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

From break input sources to TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

From HSE, HSI, LSE, LSI, MCO, RTC to TIM . . . . . . . . . . . . . . . . . . . 121

From TIM and EXTI to DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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Contents

From TIM to IRTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

9.1

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

9.1.1

9.1.2

9.1.3

Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

RTC domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Timers (TIMx) clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

I2S clock (only in STM32F303xB/C/D/E, STM32F358xC and

STM32F398xE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Internal/external clock measurement with TIM16 . . . . . . . . . . . . . . . . 135

9.2

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.2.6

9.2.7

9.2.8

9.2.9

9.2.10

9.2.11

9.2.12

9.2.13

9.2.14

9.3

9.4

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

9.4.1

9.4.2

9.4.3

9.4.4

9.4.5

9.4.6

9.4.7

9.4.8

9.4.9

9.4.10

9.4.11

9.4.12

Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 138

Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 144

APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 146

AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 148

APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 150

APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 152

RTC domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . . . 155

Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 158

Clock configuration register 2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 159

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STM32F303VDH6 Related Products

	STM32F303VDH6	STM32F303ZDT6	STM32F303VEH6	STM32F303VET6	STM32F303VEY6TR	STM32F303VET7	STM32F303VET6TR	STM32F303R8T6TR
Description	ARM Microcontrollers - MCU Analog and DSP with FPU ARM Cortex-M4 MCU with 512 Kbytes Flash, 72 MHz CPU, MPU, CCM, 12-bit ADC 5 MSPS, PGA, comparators	ARM Microcontrollers - MCU 16/32-BITS MICROS	Mainstream Mixed signals MCUs Arm Cortex-M4 core with DSP and FPU, 512 Kbytes of Flash memory, 72 MHz CPU, MPU, CCM, 12-bit ADC 5 MSPS, PGA, comparators	Antennas 2G/3G Cell SMT	Mainstream Mixed signals MCUs Arm Cortex-M4 core with DSP and FPU, 512 Kbytes of Flash memory, 72 MHz CPU, MPU, CCM, 12-bit ADC 5 MSPS, PGA, comparators	Mainstream Mixed signals MCUs Arm Cortex-M4 core with DSP and FPU, 512 Kbytes of Flash memory, 72 MHz CPU, MPU, CCM, 12-bit ADC 5 MSPS, PGA, comparators	Mainstream Mixed signals MCUs Arm Cortex-M4 core with DSP and FPU, 512 Kbytes of Flash memory, 72 MHz CPU, MPU, CCM, 12-bit ADC 5 MSPS, PGA, comparators	IC MCU 32BIT 64KB FLASH 64LQFP
speed	-	-	72 MHz	-	72 MHz	72 MHz	72 MHz	72MHz

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[TI recommended course] #Boost and buck-boost DCDC converters help wireless charging design#: //training.eeworld.com.cn/TI/show/course/5501...; xiyue521 TI Technology Forum

[Repost] Analysis of what faults may occur in switching power supplies due to capacitor damage: [align=left][color=rgb(25, 25, 25)][font="]At present, switching power supply has gradually entered our daily life and production. With the advantages of energy saving, environmental protection and hi...; 皇华Ameya360 Power technology

Some cases of DSP program crash (flying away) - hardware reasons: [size=4]DSP is different from FPGA. Programs running on DSP may crash, that is, run away. Checking crashes is basically what every DSP or embedded engineer will experience when debugging. DSP crashes ...; Aguilera DSP and ARM Processors

Milliohm meter based on [EVAL-ADICUP360] - Programming: The lower computer mainly outputs 1mA constant current to AIN5, but I don't know why the output current is inaccurate. When it is within 200uA, the actual measurement is very accurate, but when it exc...; fxyc87 DigiKey Technology Zone

stm32+Lwip protocol: The ERR value returned by udp sending is ERR_IF. What is the general reason?: When using stm32F407 + lwip-1.3.1 communication without an operating system, suddenly the return value of udp sending data is always = ERR_IF; This ERR_IF is explained by an error in the underlying ne...; haoLn stm32/stm8

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