Freescale Semiconductor
Advance Information
Document Number: MC33800
Rev. 5.0, 10/2007
Engine Control Integrated
Circuit
The 33800 is a combination output switch and driver Integrated
Circuit (IC) which can be used in numerous powertrain applications.
The IC contains two programmable constant current drivers (CCD),
an octal, low side, serial switch (OSS), and six, external MOSFET
gate pre-drivers (GD). The IC has over-voltage, under-voltage, and
thermal protection. All drivers and switches, including the external
MOSFETs, have over-current protection, off-state open load
detection, on-state shorted load detection, and fault annunciation via
the serial peripheral interface (SPI).
Additional features include: Low power Sleep Mode, Heated
Exhaust Gas Oxygen (HEGO) sensor diagnostics, output control via
serial and/or parallel inputs, PWM capability, and programmable
current output with dithering. These features, along with cost effective
packaging, make the 33800 ideal for Powertrain Engine Control
applications.
Features
•
•
•
•
•
•
•
•
•
•
•
Wide operating voltage range, 5 < VPWR < 36V
Interfaces to 3.3V and 5V microprocessors via SPI protocol
Low, Sleep Mode, standby current, typically 10uA.
Internal or external voltage reference
Internal oscillator with calibrate capability
Measures resistance to monitor HEGO sensors
CCDs have programmable current, dither frequency and amplitude
OSSs can be paralleled to increase current capability
GDs have programmable frequency and duty cycle PWM
All outputs controllable via serial and/or parallel inputs
Pb-free packaging designated by suffix code EK
V
BAT
33800
ENGINE CONTROL
EK SUFFIX (Pb-FREE)
98ASA99334D
54-PIN SOICW-EP
ORDERING INFORMATION
Device
MCZ33800EK/R2
Temperature
Range (T
A
)
-40°C to 125°C
Package
54 SOICW EP
33800
V
DD
VPWR
2.5V
VDD
VCAL
RI_REF
REXT
SI
SCLK
CS
SO
DEFAULT
EN
AN0
V
PWR
MCU
CCD1_REC
CCD1_OUT
V
PWR
CCD2_REC
CCD2_OUT
V
BAT
V
BAT
OUT1
OUT8
MOSI
SCLK
CS
MISO
{
{
VDSNS1
GD1
LRFDBK
P1,P3,P5,P7
PWM1
PWM6
GND
VSSNS123
VDSNS6
GD6
VSSNS456
Figure 1. MC33800 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
VDD
GND
VCAL
V
DD
15µA
15µA
VPWR, VDD
POR
Sleep PWR
Oscillator
Bandgap
CCD2 Outputs
CCD1 Outputs
53V
80µA
CCD2_OUT
CCD1_OUT
CCD2_REC
CCD1_REC
DEFAULT
EN
100K
P1
15µA
P3
15µA
P5
15µA
P7
15µA
SI
V
DD
+
–
lLimit
Gate Control
Open/Short
RS
40µA
CCGND
CCGND
Outputs 1 to 8
53V
75µA
OUT 1
to
Logic Control &
SPI Interface
Gate Control
Open/Short
+
–
lLimit
OUT 8
R
S
PGND
PGND
PGND
VDSNS1
15µA
15µA
CS
SCLK
SO
PWM1
15µA
PWM2
15µA
PWM3
15µA
PWM4
15µA
PWM5
15µA
Predriver1,2,3
V
PWR
Gate Drive
Control &
Diagnostics
GD1
VSSNS123
Predriver4,5,6
V
PWR
Gate Drive
Control &
Diagnostics
VDSNS4
GD4
VSSNS456
+
Differential
Amplifier
PWM6
15µA
VCAL
+
−
−
+
−
LRFDBK
VCAL
+
−
RI_REF
REXT
Exposed
Pad
Figure 2. 33800 Simplified Internal Block Diagram
33800
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
VDSNS4
GD4
VDSNS5
GD5
VDSNS6
GD6
VSSNS456
LRFDBK
SI
SCLK
CS
P1
P3
P5
P7
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
CCD2_GND
CCD2_OUT
CCD2_REC
EN
RI_REF
CCD1_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDSNS3
GD3
VDSNS2
GD2
VDSNS1
GD1
VSSNS123
REXT
PGND1
OUT1
PGND2
OUT2
OUT3
OUT4
OUT5
PGND
OUT6
OUT7
OUT8
DEFAULT
SO
VDD
VCAL
GND
VPWR
CCD1_GND
CCD1_REC
Figure 3. 33800 Pin Connections
Table 1. 33800 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 16.
Pin Number
1, 3, 5, 50,
52, 54
2, 4, 6, 49,
51, 53
7
48
8
9
Pin Name
VDSNS1-
VDSNS6
GD1-GD6
VSSNS456
VSSNS123
LRFDBK
SI
Output
Input
Output
Input
Gate Driver Output
Pin Function
Input
Formal Name
Drain Voltage Sense
Definition
The VDSNS pin is used to monitor the drain voltage of the external
MOSFET.
The GD pin provides gate drive for an external MOSFET
Source Voltage Sense The VSSNS pins are used to monitor the source voltage of the external
MOSFETS.
Load Resistance
Feedback
Serial Input Data
The LRFDBK pin is an operational amplifier output.
The SI input pin is used to receive serial data from the MCU. The serial
input data is latched on the rising edge of SCLK, and the input data
transitions on the falling edge of SCLK.
The SCLK input pin is used to clock in and out the serial data on the SI
and SO Pins while being addressed by the CS.
The Chip Select input pin is an active low signal sent by the MCU to
indicate that the device is being addressed. This input requires CMOS
logic levels and has an internal active pull up current source.
Input control of OSS output 1. When configured via the SPI, P1 input may
be used to control OSS output 1 and output 2 in parallel.
Input control of OSS output 3. When configured via the SPI, P3 input may
be used to control OSS output 3 and output 4 in parallel.
Input control of OSS output 5. When configured via the SPI, P5 input may
be used to control OSS output 5 and output 6 in parallel.
10
11
SCLK
CS
Input
Input
Serial Clock Input
Chip Select
12
13
14
P1
P3
P5
Input
Input
Input
Input One
Input Three
Input Five
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33800 Pin Definitions(continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 16.
Pin Number
15
16,17, 18, 19,
20, 21
22
23
Pin Name
P7
PWMX
Pin Function
Input
Input
Formal Name
Input Seven
Pulse Width
Modulated Input
CCD2 Ground
Current Controlled
Driver 2 Output
Current Controlled
Driver 2 Recirculation
Input
Definition
Input control of OSS output 7. When configured via the SPI, P7 input may
be used to control OSS output 7 and output 8 in parallel.
The PWMX input pin is used for direct parallel control of the GDX (Gate
Drive Output X) predriver or as on/off control of the internal PWM
controller. Control strategy is programmed via the SPI.
The CCD2_GND pin provides a dedicated ground for the CCD2 constant
current controller
The CCD2_OUT pin is connected to a series internal sense resistor and
power MOSFET driver. The CCD2_OUT has a pull up and pull down
current source and is used for fault threshold monitoring.
The CCD2_REC pin provides a recirculation path for the load current.
The CCD2_REC pin is connected to the node between the internal sense
resistor and power MOSFET driver. The device uses the differential
voltage between CCD2_REC and CCD2_OUT to determine the load
solenoid current.
The EN pin is an active high input.
The RI_REF pin is used to generate a reference current. The reference
is used in the regulation of the constant current controller. The constant
current controller regulation current is inversely proportional to the
reference current through the external resistor. A 39.2kΩ 1% resistor to
ground will set the 1FF programmed current value of the CCD1 to
1075mA and the CCD2 to be 232mA.
The CCD1_OUT pin is connected to a series internal sense resistor and
power MOSFET driver. The CCD1_OUT has a pull up and pull down
current source and is used for fault threshold monitoring.
The CCD1_REC pin provides a recirculation path for the load current.
The CCD1_REC pin is connected to the node between the internal sense
resistor and power MOSFET driver. The device uses the differential
voltage between CCD1_REC and CCD1_OUT to determine the load
solenoid current.
The CCD1_GND pin provides a dedicated ground for the CCD1 constant
current controller
CCD2_GND
CCD2_OUT
Ground
Output
24
CCD2_REC
Input
25
26
EN
RI_REF
Input
Output
ENABLE
Resistor for Current
Reference
27
CCD1_OUT
Output
Current Controlled
Driver 1 Output
Current Controlled
Driver 1 Recirculation
Input
28
CCD1_REC
Input
29
30
31
32
CCD1_GND
VPWR
GND
VCAL
Ground
CCD1 Ground
Power Input Analog Voltage Supply The VPWR pin provides power to all pre-driver, driver and output circuits
and other internal functions such as the oscillator and SPI circuits.
Ground
Input
Ground
Voltage Calibrated
Input
Analog ground for the internal control circuits of the IC. This ground
should be used for decoupling of VDD and VPWR supply.
VCAL input is a precision (2.5V, +8.0mV, -20mV over temperature)
reference input, used in several internal circuits. A 1.0nF to 10nF
decoupling capacitor is required on the VCAL input pin to ground.
The VDD pin supplies power to the Serial Output (SO) buffer along with
the pull up current sources for the chip select (CS) and DEFAULT inputs.
The SO output pin is used to transmit serial data from the device to the
MCU. The SO pin remains tri-stated until selected by the active low CS.
The serial output data is available to be latched by the MCU on the rising
edge of SCLK. The SO data transitions on falling edge of the SCLK.
The DEFAULT pin is an active high input.
Octal Serial Switch (OSS) low side driver output 1-8.
33
34
VDD
SO
Power Input Digital Voltage Supply
Output
Serial Output Data
35
36-38, 40,
41-43, 45
DEFAULT
OUT1-OUT8
Input
Output
Default Mode Enable
OSS Output 1-8
33800
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 1. 33800 Pin Definitions(continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 16.
Pin Number
39
44
46
47
_
Pin Name
PGND3
PGND2
PGND1
REXT
_
Pin Function
Ground
Ground
Ground
Output
Ground
Formal Name
OSS 3-8 Ground
OSS 2 Ground
OSS 1 Ground
Resistor External
Reference
Exposed Pad Ground
Definition
This PGND pins provide a dedicated ground for the Octal Serial Switch
(OSS) low side driver outputs 3 - 8.
This PGND pin provides a dedicated ground for the Octal Serial Switch
(OSS) low side driver output 2.
This PGND pin provides a dedicated ground for the Octal Serial Switch
(OSS) low side driver output 1.
The REXT pin is used to generate a reference current.
The package exposed pad provides thermal conductivity for the die and
should be grounded to system ground.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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