Analog, Mixed-Signal and Power Management
MC33903/4/5
System Basis Chip Gen2 with High Speed CAN and
LIN Interface
Overview
The MC33903/4/5 is the second generation
family of System Basis Chips, which combine
several features and enhance present module
designs. The device works as an advanced
power management unit for the MCU and
additional integrated circuits such as sensors
and CAN transceivers. It has a built-in enhanced
high speed CAN interface (ISO11898-2 and -5),
with local and bus failure diagnostics, protection,
and fail safe operation mode. The SBC may
include one or two LIN 2.1/J2602-2 interfaces
with LIN master terminal outputs. It includes
wake-up input pins than can also be configured
as output drivers for flexibility.
This device implements multiple Low Power
modes with very low-current consumption. In
addition, the device is part of a family concept
where pin compatibility, among the various
devices with and without LIN interfaces, adds
versatility to module design.
The MC33903/4/5 also implements an
innovative and advanced fail-safe state machine
and concept solution. This family of devices are
supported by an enablement ecosystem that
includes an evaluation board, software interface,
EMC/ESD conformance reports and training
material that allows a faster time to market and
eases your designs.
MC33903/4/5 Block Diagram
MCU Voltage Regulator (V
DD
)
Internal CAN Regulator (V
CAN
)
Legend
Low Power Modes
Flexible (I/O)
SPI Adv W/D
33903
33903S
33903D
33904
33905S
33905D
Power Sharing (V
DD
BALLAST)
Ballast Regulator (V
AUX
)
LIN 1
LIN 2
Secured State Machine
CAN High Speed
Power Management Scalability
• MCU power supply (V
DD
): 5.0 or 3.3 V /
150 mA (power split option for scalable
needs - up to 300 mA)
• 5.0 or 3.3 V voltage regulator (V
AUX
) for
auxiliary loads
• Dedicated 5.0 V voltage regulator (5 V
CAN) for High Speed CAN
Functional Safety
• Innovative cranking pulse management
during V
DD
low
• Fail safe & configurable state machine
• Enhanced protections and diagnostics
Energy Savings
• Ultra low power modes (typ 15 µA with
V
DD
off)
• Innovative Wake-up management and
cyclic sense capability
Robust Physical Layers
• Certification to LIN 2.1, J2602-2, and
ISO11898-2-5 standards
• Successfully certified for stringent EMC,
ISO, and ESD standards
Easy to Use
• Ecosystem to lower development time and
simplify access
• Debug mode to save time during
application development
Flexibility & Compatibility:
• Selectable parameters (RST time, W/D
type, VDD under-voltage threshold, V
AUX
3.3 or 5.0 V)
• 1 or 2 LIN options (33903S, 33905S and
33903D, 33905D)
• Scalable (I/O pins configurable as wake-up
inputs or output LIN master terminations)
IDEAL COMPANION CHIP FOR MCU IN BODY, SAFETY, AND POWERTRAIN APPLICATIONS
Segment
Body
Body Controller
Gateway
Seat Module
Door Module
Lighting Control Module
Column Module
HVAC
Cluster
Safety & Chassis
Seat Belt Pre-tensioner
Electric Parking Brake
Steering
Power Train
Fuel Pump
Water Pump
Glow Plug
Engine Management Low End
Key Characteristics
Parameter
MCU Linear V
REG
(LDO)
Output Current
Bus Output
33903D/S, 33905D/S only
Data Rate
CAN
LIN
Low Power V
DD
OFF/ V
DD
ON Current
ESD - Module Level (CAN and LIN)
Operating Voltage
Maximum Input Voltage
Operating Temperature
40 kB/s – 1.0 MB/s
10.4 kB/s – 20 kB/s (100 kB/s in fast mode)
15/25 µA
±8000 V
5.5 - 28 V
27 VDC, 40 V (Load Dump)
-40 °C<T
A
<125 °C
Characterization
5.0 / 3.3 V
(300 mA for 33903D/S, 33904, 33905D/S with optional external PNP implementation)
CAN
LIN
S12x, MPC563x
S12x, S08x
S12x, MPC560x
S12x, MPC560x, S08x
S12x, MPC560x
Applications
Proposed FSL MCU
MC33905D Simplified Application Drawing
V
BAT
D1
Q2
(5.0 V/3.3 V)
Q1
Features
• LDO Linear Power Supply 5.0 or 3.3 V, up to 300 mA with an optional external ballast
transistor
VDD
VBAUX
VCAUX VAUX VSUP1
VE
VB
VSUP2
5 V Auxiliary
Regulator
V
S2-INT
• LDO Auxiliary Regulator with ballast transistor (5.0 / 3.3 V configurable)
• Under-voltage management for cranking
• Internal 5.0 V regulator for CAN driver supply
• Low current consumption in sleep mode
• Fail safe state machine linked with SAFE pin
• Secured SPI with Watchdog capability
• High precision V
SUP
sense monitoring
• Multiple Analog sensing to 1 MUX output
• Dual configurable I/O with W/U feature
• “B” versions are recommended for new designs. Changes implemented on “B”
versions: resolved V
SUP
slow ramp up behavior, enhanced device current
consumption, and improved oscillator
• CAN, ISO11898-2 and 11898-5 compliant
• 2 LIN transceivers - 2.0, 2.1, and SAE J2602-2 compliant
V
DD
Regulator
RST
SAFE
Fail-safe
DBG
GND
INT
MOSI
Power Management
Oscillator
State Machine
SPI
SCLK
MISO
CS
MUX-OUT
VSENSE
Analog Monitoring
Signals Condition & Analog MUX
V
S2-INT
I/O-0
I/O-1
CANH
SPLIT
CAN Bus
Configurable
Input-Output
5 V-CAN
Regulator
5V-CAN
Enhanced High-speed CAN
Physical Interface
V
S2-INT
TXD
RXD
TXD-L1
CANL
LIN Bus
LIN-TERM1
LIN-1
LIN Interface - #1
V
S2-INT
RXD-L1
TXD-L2
LIN Bus
LIN-TERM2
LIN-2
LIN Interface - #2
RXD-L2
Freescale Part Number
MC33905D (Dual LIN)
MCZ33905BD3EK/R2
MCZ33905CD3EK/R2
MCZ33905D5EK/R2
MCZ33905BD5EK/R2
MCZ33905CD5EK/R2
MC33905S (Single LIN)
MCZ33905BS3EK/R2
MCZ33905CS3EK/R2
MCZ33905S5EK/R2
MCZ33905BS5EK/R2
MCZ33905CS5EK/R2
V
DD
output
voltage
CAN
interface
LIN
interface(s)
I/O Wake-up Capability
V
AUX
V
SENSE
MUX
Package
3.3 V
1
5.0 V
2
2 wake-up + 2 LIN terms
or
3 wake-up + 1 LIN terms
or
4 wake-up + no LIN terms
Yes
Yes
Yes
SOIC 54 pins
exposed pad
3.3 V
3 Wake-up + 1 LIN terms
1
5.0 V
1
or
4 Wake-up + no LIN terms
Yes
Yes
Yes
SOIC 32 pin
exposed pad
MC33905S Simplified Application Drawing
V
BAT
D1
Q2
(5.0 V/3.3 V)
Q1
Features
• LDO Linear Power Supply 5.0 or 3.3 V, up to 300 mA with an optional external ballast
transistor
• LDO Auxiliary Regulator with ballast transistor (5.0 / 3.3 V configurable)
VDD
VBAUX
VCAUX VAUX VSUP1
VE VB
VSUP2
5 V Auxiliary
Regulator
V
S2-INT
V
DD
Regulator
• Under voltage management for cranking
• Internal 5.0 V regulator for CAN driver supply
• Low current consumption in sleep mode
• Fail safe state machine linked with SAFE pin
• Secured SPI with Watchdog capability
• High precision V
SUP
sense monitoring
• Multiple Analog sensing to 1 MUX output
• Triple configurable I/O with W/U feature
• “B” versions are recommended for new designs. Changes implemented on “B”
versions: resolved V
SUP
slow ramp up behavior, enhanced device current
consumption, and improved oscillator
• CAN, ISO11898-2 and 11898-5 compliant
• 1 LIN transceiver - 2.0, 2.1, and SAE J2602-2 compliant
SAFE
RST
Fail-safe
DBG
GND
INT
MOSI
Power Management
Oscillator
State Machine
SPI
SCLK
MISO
CS
MUX-OUT
VSENSE
Analog Monitoring
Signals Condition & Analog MUX
V
S2-INT
I/O-0
V
BAT
I/O-1
I/O-3
CANH
SPLIT
Configurable
Input-Output
5 V-CAN
Regulator
5V-CAN
Enhanced High-speed CAN
Physical Interface
V
S2-INT
TXD
RXD
CAN Bus
CANL
LIN Term
LIN Bus
TXD-L
LIN-T
LIN
LIN Interface
RXD-L
MC33904 Simplified Application Drawing
V
BAT
D1
Features
Q2
(5.0 V/3.3 V)
Q1
VBAUX
VCAUX VAUX VSUP1
VE VB
• LDO Linear Power Supply 5.0 or 3.3 V, up to 300 mA with an optional external ballast
transistor
• LDO Auxiliary Regulator with ballast transistor (5.0 / 3.3 V configurable)
VDD
VSUP2
5 V Auxiliary
Regulator
V
S2-INT
V
DD
Regulator
• Under-voltage management for cranking
• Internal 5.0 V regulator for CAN driver supply
• Low current consumption in sleep mode
• Fail safe state machine linked with SAFE pin
• Secured SPI with Watchdog capability
• High precision V
SUP
sense monitoring
• Multiple Analog sensing to 1 MUX output
• Quad configurable I/O with W/U feature
• “B” versions are recommended for new designs. Changes implemented on “B”
versions: resolved V
SUP
slow ramp up behavior, enhanced device current
consumption, and improved oscillator
• CAN transceiver: ISO11898-2 and 11898-5 compliant
SAFE
RST
Fail Safe
DBG
GND
VSENSE
INT
MOSI
Power Management
Oscillator
State Machine
SPI
SCLK
MISO
CS
MUX-OUT
Analog Monitoring
Signals Condition & Analog MUX
V
BAT
I/O-0
I/O-1
I/O-2
I/O-3
Configurable
Input-Output
V
S2-INT
5V-CAN
Regulator
5V-CAN
CANH
SPLIT
CAN Bus
Enhanced High Speed CAN
Physical Interface
TxD
RXD
CANL
Freescale Part Number
MC33904
MCZ33904B3EK/R2
MCZ33904C3EK/R2
MCZ33904A5EK/R2
MCZ33904B5EK/R2
MCZ33904C5EK/R2
V
DD
output
voltage
CAN
interface
LIN
interface(s)
I/O Wake-up Capability
V
AUX
V
SENSE
MUX
Package
3.3 V
SOIC 32 pins
exposed pad
1
5.0 V
0
4 Wake-up
Yes
Yes
Yes
MC33903 Simplified Application Drawing
VSUP1
Features
• LDO Linear Power Supply 5.0 or 3.3 V
VSUP2
V
S-INT
SAFE
V
DD
Regulator
VDD
RST
INT
• V
DD
does not allow usage of an external PNP on the 33903. Output current limited to
150 mA
• Under-voltage management for cranking
• Internal 5.0 V regulator for CAN driver supply
• Low current consumption in sleep mode
• Fail safe state machine linked with SAFE pin
• Secured SPI with Watchdog capability
• Configurable I/O with W/U feature
• “B” versions are recommended for new designs. Changes implemented on “B”
versions: resolved V
SUP
slow ramp up behavior, enhanced device current
consumption, and improved oscillator
• CAN transceiver: ISO11898-2 and 11898-5 compliant
Power Management
DBG
GND
MOSI
State Machine
SPI
SCLK
MISO
CS
Oscillator
Configurable
Input-Output
V
S-INT
I/O-0
5 V-CAN
Regulator
5 V-CAN
CANH
SPLIT
CANL
Enhanced High Speed CAN
Physical Interface
TxD
RXD
Freescale Part Number
MC33903
MCZ33903B3EK/R2
MCZ33903C3EK/R2
MCZ33903B5EK/R2
MCZ33903C5EK/R2
V
DD
output
voltage
CAN
interface
LIN
interface(s)
I/O Wake-up Capability
V
AUX
V
SENSE
MUX
Package
3.3 V
1
5.0 V
0
1 Wake-up
No
No
No
SOIC 32 pins
exposed pad
MC33903D Simplified Application Drawing
VSUP
VE
VB
Features
• LDO Linear Power Supply 5.0 or 3.3 V, up to 300 mA with an optional
external ballast transistor
• Under-voltage management for cranking
RST
V
S2-INT
SAFE
V
DD
Regulator
VDD
Fail-safe
DBG
GND
VSENSE
• Internal 5.0 V regulator for CAN driver supply
• Low current consumption in sleep mode
• Fail safe state machine linked with SAFE pin
• Secured SPI with Watchdog capability
• High precision V
SUP
sense monitoring
• Multiple Analog sensing to 1 MUX output
• Configurable I/O with W/U feature
• “B” versions are recommended for new designs. Changes implemented on
“B” versions: resolved V
SUP
slow ramp up behavior, enhanced device
current consumption, and improved oscillator
• CAN, ISO11898-2 and 11898-5 compliant
• 2 LIN transceivers - 2.0, 2.1, and SAE J2602-2 compliant
INT
MOSI
Power Management
Oscillator
State Machine
SPI
SCLK
MISO
CS
Analog Monitoring
Signals Condition & Analog MUX
MUX-OUT
IO-0
V
S2-INT
Configurable
Input-Output
5 V-CAN
Regulator
5 V-CAN
CANH
SPLIT
CANL
V
S2-INT
TXD-L1
LIN-T1
LIN-1
LIN-T2
LIN-2
V
S2-INT
TXD-L2
Enhanced High-speed CAN
Physical Interface
TXD
RXD
LIN 2.1 Interface - #1
RXD-L1
LIN 2.1 Interface - #2
RXD-L2
Freescale Part Number
MC33903D (Dual LIN)
MCZ33903BD3EK/R2
MCZ33903CD3EK/R2
MCZ33903BD5EK/R2
MCZ33903CD5EK/R2
V
DD
output
voltage
CAN
interface
LIN
interface(s)
I/O Wake-up Capability
V
AUX
V
SENSE
MUX
Package
3.3 V
1
5.0 V
2
1 wake-up + 2 LIN terms
or
2 wake-up + 1 LIN terms
or
3 wake-up + no LIN terms
No
Yes
Yes
SOIC 32 pins
exposed pad
MC33903S Simplified Application Drawing
VSUP
VE VB
Features
VDD
V
S-INT
V
DD
Regulator
• LDO Linear Power Supply 5.0 or 3.3 V, up to 300 mA with an optional
external ballast transistor
• Under-voltage management for cranking
• Internal 5.0 V regulator for CAN driver supply
• Low current consumption in sleep mode
• Fail safe state machine linked with SAFE pin
• Secured SPI with Watchdog capability
• High precision V
SUP
sense monitoring
• Multiple Analog sensing to 1 MUX output
• Configurable I/O with W/U feature
• “B” versions are recommended for new designs. Changes implemented on
“B” versions: resolved V
SUP
slow ramp up behavior, enhanced device
current consumption, and improved oscillator
• CAN, ISO11898-2 and 11898-5 compliant
• 1 LIN transceiver - 2.0, 2.1, and SAE J2602-2 compliant
SAFE
RST
Fail Safe
DBG
GND
VSENSE
INT
MOSI
Power Management
Oscillator
State Machine
SPI
SCLK
MISO
CS
Analog Monitoring
Signals Condition & Analog MUX
V
S-INT
MUX-OUT
I/O-0
I/O-3
CANH
SPLIT
CANL
V
S-INT
LIN-T
LIN
Configurable
Input-Output
5 V-CAN
Regulator
5 V-CAN
Enhanced High Speed CAN
Physical Interface
TXD
RXD
LIN Term #1
TXD-L
LIN 2.1 Interface - #1
RXD-L
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