MT9M034
MT9M034 1/3-Inch CMOS
Digital Image Sensor
Table 1. KEY PARAMETERS
Parameter
Optical Format
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Input Clock Range
Output Clock Maximum
Output
Frame Rate
Parallel
Full Resolution
720p
Responsivity
SNR
MAX
Maximum Dynamic Range
Supply Voltage
I/O
Digital
Analog
Power Consumption
Value
1/3−inch (6 mm)
1280
×
960 = 1.2 Mp
3.75
μm
RGB Bayer or Monochrome
Electronic Rolling Shutter
6–50 MHz
74.25 MHz
12−bit
45 fps
60 fps
5.48 V/lux−sec
43.9 dB
>115 dB
1.8 V* or 2.8 V
1.8 V
2.8 V
270 mW (1280
×
720
60 fps Parallel Output Linear
Mode)
460 mW (1280
×
720 60 fps
Parallel Output HDR Mode)
–30°C to + 70°C (Surveillance)
10×10 mm 48−pin iLCC
Bare Die
*1.8 V VDD_IO is recommended due to better row noise performance
ILCC48 10x10
CASE 847AD
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ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Applications
•
Video Surveillance
•
720p60 Video Applications
•
High Dynamic Range Imaging
Operating Temperature (ambient)
−T
A
Package Options
Features
•
•
•
•
•
•
•
•
•
Superior Low−light performance
HD Video (720p60)
Linear or High Dynamic Range Capture
Video/Single Frame Modes
On−chip AE and Statistics Engine
Parallel and Serial Output
Auto Black Level Calibration
Context Switching
Temperature Sensor
©
Semiconductor Components Industries, LLC, 2010
May, 2017
−
Rev. 9
1
Publication Order Number:
MT9M034/D
MT9M034
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
MT9M034I12STC−DPBR1
MT9M034I12STC−DRBR1
MT9M034I12STM−DPBR1
MT9M034I12STM−DRBR
Product Description
1.2 MP 1/3” CIS
1.2 MP 1/3” CIS
1.2 MP 1/3” CIS
1.2 MP 1/3” CIS
Orderable Product Attribute Description
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
GENERAL DESCRIPTION
The ON Semiconductor MT9M034 is a 1/3−inch CMOS
digital image sensor with an active−pixel array of 1280 (H)
×
960 (V). It captures images in either linear or high dynamic
range modes, with a rolling−shutter readout. It includes
sophisticated camera functions such as auto exposure
control, windowing, and both video and single frame modes.
It is designed for both low light and high dynamic range
scene performance. It is programmable through a simple
two−wire serial interface. The MT9M034 produces
extraordinarily clear, sharp digital pictures, and its ability to
capture both continuous video and single frames makes it the
perfect choice for a wide range of applications, including
surveillance and HD video.
The ON Semiconductor MT9M034 can be operated in its
default mode or programmed for frame size, exposure, gain,
and other parameters. The default mode output is a
960p−resolution image at 45 frames per second (fps). In
linear mode, it outputs 12−bit raw data. In high dynamic
range mode, it outputs 12−bit compressed data using parallel
output. The device may be operated in video (master) mode
or in single frame trigger mode.
FRAME_VALID and LINE_VALID signals are output on
dedicated pins, along with a synchronized pixel clock in
parallel mode.
The MT9M034 includes additional features to allow
application−specific tuning: windowing and offset,
adjustable auto−exposure control, auto black level
correction, and on−board temperature sensor. Optional
register information and histogram statistic information can
be embedded in first and last 2 lines of the image frame.
The sensor is designed to operate in a wide temperature
range (–30°C to +70°C).
FUNCTIONAL OVERVIEW
The MT9M034 is a progressive−scan sensor that
generates a stream of pixel data at a constant frame rate. It
uses an on−chip, phase−locked loop (PLL) that can be
optionally enabled to generate all internal clocks from a
single master input clock running between 6 and 50 MHz
The maximum output pixel rate is 74.25 Mp/s,
corresponding to a clock rate of 74.25 MHz. Figure 1 shows
a block diagram of the sensor.
OTPM
Active Pixel Sensor
(APS)
Array
Power
Timing and Control
(Sequencer)
Memory
PLL
External
Clock
Auto Exposure
and Stats Engine
Pixel Data Path
Analog Processing and
A/D Conversion
Trigger
Two−Wire
Serial
Interface
(Signal Processing)
Parallel
Output
Control Registers
Figure 1. Block Diagram
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MT9M034
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 1.2 Mp Active− Pixel Sensor array. The timing
and control circuitry sequences through the rows of the
array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog−to−digital converter (ADC). The output from the
ADC is a 12−bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain). The sensor also offers a high dynamic range
mode of operation where multiple images are combined
on−chip to produce a single image at 20−bit per pixel value.
A compressing mode is further offered to allow this 20−bit
pixel value to be transmitted to the host system as a 12−bit
value with close to zero loss in image quality. The pixel data
are output at a rate of up to 74.25 Mp/s, in parallel to frame
and line synchronization signals.
PLL
Analog Analog
Power
1
Power
1
Power
1
Digital
Digital I/0 Core
Power
1
Power
1
1.5kΩ
2
Master clock
(6–50 MHz)
1.5kΩ
2,3
V
DD
_IO V
DD
V
DD
_PLL V
AA
VAA_PIX
EXTCLK
S
ADDR
S
DATA
SCLK
TRIGGER
OE_BAR
STANDBY
RESET_BAR
TEST
D
GND
D
OUT
[11:0]
PIXCLK
LINE_VALID
FRAME_VALID
To
Controller
From
Controller
A
GND
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
V
AA
_PIX
Digital
ground
Analog
ground
Notes:
1.
2.
3.
4.
All power supplies should be adequately decoupled.
ON Semiconductor recommends a resistor value of 1.5 kΩ, but a greater value may be used for slower two-wire speed.
The serial interface output pads and V
DD
SLVS can be left unconnected if the parallel output interface is used.
ON Semiconductor recommends that 0.1
μF
and 10
μF
decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design considerations.
Check the demo headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
power planes is minimized.
6. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage currents.
7. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output interface is used.
Figure 2. Typical Configuration: Parallel Pixel Data Interface
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MT9M034
6
5
4
V
DD
_PLL
3
2
1
48
47
46
45
44
43
EXTCLK
D
OUT
6
D
OUT
5
D
OUT
4
D
OUT
3
D
OUT
2
D
OUT
1
D
OUT
0
D
GND
D
GND
NC
7
8
9
10
11
12
13
14
15
16
17
18
D
OUT
7
D
OUT
8
D
OUT
9
D
OUT
10
D
OUT
11
V
DD
_IO
PIXCLK
V
DD
S
CLK
S
DATA
RESET_BAR
V
DD
_IO
FRAME_VALID
NC
NC
V
AA
A
GND
V
AA
_PIX
V
AA
_PIX
V
AA
A
GND
V
AA
Reserved
Reserved
Reserved
42
41
40
39
38
37
36
35
34
33
32
31
LINE_VALID
29
STANDBY
TRIGGER
OE_BAR
FLASH
S
ADDR
TEST
19
20
21
22
23
24
25
26
27
28
Figure 3. 48 iLCC Package, Parallel Output
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D
GND
30
V
DD
NC
NC
MT9M034
Table 3. PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Name
D
OUT
4
D
OUT
5
D
OUT
6
V
DD
_PLL
EXTCLK
D
GND
D
OUT
7
D
OUT
8
D
OUT
9
D
OUT
10
D
OUT
11
V
DD_
IO
Type
Output
Output
Output
Power
Input
Power
Output
Output
Output
Output
Output
Power
Output
Power
Input
I/O
Input
Power
Power
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
PLL power
External input clock
Digital ground
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output (MSB)
I/O supply power
Pixel clock out. D
OUT
is valid on rising edge of this clock
Digital power
Two−Wire Serial clock input
Two−Wire Serial data I/O
Asynchronous reset (active LOW). All settings are restored to
factory default
I/O supply power
Digital power
Description
PIXCLK
V
DD
S
CLK
S
DATA
RESET
_
BAR
V
DD_
IO
V
DD
NC
NC
STANDBY
OE_BAR
S
ADDR
TEST
FLASH
TRIGGER
FRAME_VALID
LINE_VALID
D
GND
Reserved
Reserved
Reserved
V
AA
A
GND
V
AA
V
AA_
PIX
V
AA_
PIX
A
GND
Power
Power
Power
Power
Power
Power
Input
Input
Input
Input
Output
Input
Output
Output
Power
Standby−mode enable pin (active HIGH)
Output enable (active LOW)
Two−Wire Serial address select
Manufacturing test enable pin (connect to D
GND
)
Flash output control
Exposure synchronization input
Asserted when D
OUT
frame data is valid
Asserted when D
OUT
line data is valid
Digital ground
NC
NC
NC
Analog power
Analog ground
Analog power
Pixel power
Pixel power
Analog ground
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