Data Sheet
FEATURES
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate V
P
allows extended tuning voltage
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the
ADF4110/ADF4111/
ADF4112/ADF4113, ADF4106, ADF4153
Programmable modulus on fractional-N synthesizer
Trade-off noise vs. spurious performance
Fast-lock mode with built-in timer
Loop filter design possible with ADIsimPLL™
Fractional-N Frequency Synthesizer
ADF4154
GENERAL DESCRIPTION
The ADF4154 is a fractional-N frequency synthesizer that
implements local oscillators in the up conversion and down
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD),
a precision charge pump, and a programmable reference divider.
There is a Σ-Δ based fractional interpolator to allow programmable
fractional-N division. The INT, FRAC, and MOD registers define
an overall N-divider (N = (INT + (FRAC/MOD))). In addition,
the 4-bit reference counter (R-counter) allows selectable REF
IN
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and a voltage-controlled oscillator (VCO).
A key feature of the ADF4154 is the fast-lock mode with a built-
in timer. The user can program a predetermined countdown
time value so that the PLL remains in wide bandwidth mode,
instead of the user having to control this time externally.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
APPLICATIONS
Base stations for mobile radio (WiMAX, PHS, GSM, PCS, DCS,
CDMA, PMR, W-CDMA, supercell 3G)
Wireless handsets (PMR, GSM, PCS, DCS, CDMA, WCDMA)
CATV equipment
Wireless LANs
Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DD
DV
DD
V
P
SDV
DD
R
SET
ADF4154
4-BIT
R COUNTER
+ PHASE
FREQUENCY
DETECTOR
–
REFERENCE
REF
IN
×2
DOUBLER
V
DD
DGND
CHARGE
PUMP
CP
HIGH Z
LOCK
DETECT
MUXOUT
OUTPUT
MUX
V
DD
R
DIV
N
DIV
THIRD ORDER
FRACTIONAL
INTERPOLATOR
FAST-LOCK
SWITCH
CURRENT
SETTING
RFCP3 RFCP2 RFCP1
N COUNTER
RF
IN
A
RF
IN
B
CLOCK
DATA
LE
24-BIT
DATA
REGISTER
FRACTION
REG
MODULUS
REG
INTEGER REG
AGND
DGND
CPGND
Figure 1.
Rev. C
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
04833-001
ADF4154* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Product Selection Guide
•
RF Source Booklet
Technical Articles
•
Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 1
•
Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 3
•
Phase-Locked Loops for High-Frequency Receivers and
Transmitters - Part 2
EVALUATION KITS
•
ADF4154 Evaluation Board
DOCUMENTATION
Application Notes
•
AN-30: Ask the Applications Engineer - PLL Synthesizers
•
AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
Data Sheet
•
ADF4154:Fractional-N Frequency Synthesizer Data Sheet
User Guides
•
UG-161: PLL Frequency Synthesizer Evaluation Board
•
UG-476: PLL Software Installation Guide
DESIGN RESOURCES
•
ADF4154 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
SOFTWARE AND SYSTEMS REQUIREMENTS
•
Fractional-N Software
DISCUSSIONS
View all ADF4154 EngineerZone Discussions.
TOOLS AND SIMULATIONS
• ADIsimPLL™
•
ADIsimRF
•
dt_ADF4x5x_Register_Configuration
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
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ADF4154
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Pin Function Descriptions ...................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description ........................................................................... 9
Reference Input Section ............................................................... 9
RF Input Stage ............................................................................... 9
RF INT Divider ............................................................................. 9
INT, FRAC, MOD, and R Relationship ..................................... 9
R-Counter ...................................................................................... 9
Phase Frequency Detector (PFD) and Charge Pump .............. 9
MUXOUT and Lock Detect ...................................................... 10
Input Shift Registers ................................................................... 10
Program Modes .......................................................................... 10
Registers ........................................................................................... 11
Data Sheet
Register Definitions ................................................................... 16
R-Divider Register, R1 ............................................................... 16
Control Register, R2 ................................................................... 16
Noise and Spur Register, R3 ...................................................... 17
Reserved Bits ............................................................................... 17
Initialization Sequence .............................................................. 18
RF Synthesizer: A Worked Example ........................................ 18
Modulus ....................................................................................... 18
Reference Doubler and Reference Divider ............................. 18
12-Bit Programmable Modulus ................................................ 18
Spurious Optimization and Fast Lock ..................................... 18
Fast-Lock Timer and Register Sequences ............................... 19
Fast Lock: An Example .............................................................. 19
Fast Lock: Loop Filter Topology ............................................... 19
Spur Mechanisms ....................................................................... 19
Spur Consistency ........................................................................ 20
Filter Design—ADIsimPLL....................................................... 20
Interfacing ................................................................................... 20
PCB Design Guidelines for Chip Scale Package .................... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
8/12—Rev. B to Rev. C
Changes to Figure 4 .......................................................................... 6
Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) .... 22
Changes to Ordering Guide .......................................................... 22
9/11—Rev. A to Rev. B
Changes to Noise Characteristics Parameter ................................ 3
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
12/06—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Applications .................................................................. 1
Changes to Functional Block Diagram .......................................... 1
Changes to Specifications ................................................................ 3
Changes to Absolute Maximum Ratings ....................................... 5
Changes to Typical Performance Characteristics Conditions .... 7
Replaced Figure 5 through Figure 7 ............................................... 7
Changes to Figure 13.........................................................................8
Changes to R-Divider Register Map ............................................ 13
Changes to Control Register Map ................................................ 14
Change to REF
IN
Doubler Section ................................................ 18
Added Initialization Sequence Section ........................................ 18
Change to 12-Bit Programmable Modulus Section ................... 18
Changes to Fast-Lock Timer and Register Sequences Section........ 19
Changes to Fast Lock: Loop Filter Topology Section ................ 19
Deleted Spurious Signal Section ................................................... 18
Added Spur Mechanisms Section ................................................ 19
Added Spur Consistency Section ................................................. 20
Change to Filter Design—ADIsimPLL Section .......................... 20
Change to Interfacing Section ...................................................... 20
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
5/04—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet
SPECIFICATIONS
ADF4154
AV
DD
= DV
DD
= SDV
DD
= 2.7 V to 3.3 V; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted; dBm
referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF Input Frequency (RF
IN
)
1
REFERENCE CHARACTERISTICS
REF
IN
Input Frequency
1
REF
IN
Input Sensitivity
REF
IN
Input Capacitance
REF
IN
Input Current
PHASE DETECTOR
Phase Detector Frequency
3
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
R
SET
Range
I
CP
Three-State Leakage Current
Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
, SDV
DD
V
P
I
DD
Low Power Sleep Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PN
SYNTH
)
4
Normalized 1/f Noise (PN
1_f
)
5
Phase Noise Performance
6
1750 MHz Output
7
1
2
B Version
0.5/4.0
1.0/4.0
10/250
0.7/AV
DD
10
±100
32
Unit
GHz min/max
GHz min/max
MHz min/max
V p-p min/max
pF max
µA max
MHz max
Test Conditions/Comments
See
Figure 15
for the input circuit.
−8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 400 V/µs.
−10 dBm/0 dBm min/max.
See
Figure 14
for input circuit.
For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave,
slew rate > 25 V/µs.
Biased at AV
DD
/2.
2
5
312.5
2.5
2.7/10
1
2
2
2
1.4
0.6
±1
10
1.4
0.4
2.7/3.3
AV
DD
AV
DD
/5.5
24
1
−220
−114
−102
mA typ
µA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
V min
V max
µA max
pF max
V min
V max
V min/V max
V min/V max
mA max
µA typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Programmable. See
Table 5
.
With R
SET
= 5.1 kΩ.
With R
SET
= 5.1 kΩ.
Sink and source current.
0.5 V < V
CP
< V
P
− 0.5 V.
0.5 V < V
CP
< V
P
− 0.5 V.
V
CP
= V
P
/2.
Open-drain 1 kΩ pull-up to 1.8 V.
I
OL
= 500 µA.
20 mA typical.
PLL loop BW = 500 kHz.
Measured at 100 kHz offset.
10 kHz offset; normalized to 1GHz.
@ VCO output.
@ 1 kHz offset, 26 MHz PFD frequency.
Use a square wave for frequencies below f
MIN
.
AC coupling ensures AV
DD
/2 bias. See Figure 14 for a typical circuit.
3
Guaranteed by design. Sample tested to ensure compliance.
4
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(F
PFD
). PN
SYNTH
= PN
TOT
− 10 log(F
PFD
) − 20 log(N).
5
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, F
RF
,
and at a frequency offset f is given by PN = PN
1_f
+ 10 log(10 kHz/f) + 20 log(F
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6
The phase noise is measured with the EVAL-ADF4154EB1 and the HP8562E spectrum analyzer.
7
f
REFIN
= 26 MHz, f
PFD
= 26 MHz, offset frequency = 1 kHz, RF
OUT
= 1750 MHz, loop B/W = 20 kHz, lowest noise mode.
Rev. C | Page 3 of 24
ADF4154
TIMING CHARACTERISTICS
Data Sheet
AV
DD
= DV
DD
= SDV
DD
= 2.7 V to 3.3 V; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted; dBm
referred to 50 Ω.
Table 2.
Parameter
1
t
1
t
2
t
3
t
4
t
5
t
6
t
7
1
Limit at T
MIN
to T
MAX
(B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
Guaranteed by design, but not production tested.
t
4
CLOCK
t
5
t
2
DATA
DB23 (MSB)
DB22
t
3
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
7
LE
t
1
LE
t
6
04833-026
Figure 2. Timing Diagram
Rev. C | Page 4 of 24
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