INSSTU32S869
INSSTUA32S869
INSSTUB32869
DDR2 Configurable
Registered Buffer
with Parity Checking
Data Sheet
Applications
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High Performance Workstations
Mid and High Performance Servers
High Reliability Systems
Features
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INSSTU32S869 meets or exceeds all JESD82-12 performance specifications up to DDR2-533 rates
INSSTUA32S869 meets or exceeds all JESDxx-x performance specifications up to DDR2-667 rates
INSSTUB32869 meets or exceeds all JESDxx-x performance specifications up to DDR2-800 rates
Supports DDR2 RDIMM module W
Single die solution for lowest input capacitance
Available in a 150-ball TFBGA “Green” Package
Complies with DDR2 SDRAM Over/Undershoot specification as defined in JESD79-2
Pull-down resistors on all data and parity inputs
Latch-up exceeds JESD78 class 2
ESD protection exceeds JESD22
Available in Industrial Temperature Range (-40 °C to +85 °C)
Description
This 14-bit 1:2 register is designed for
nominal 1.8V power supply operation. All digital
inputs are SSTL_18 compatible except for the
1.8V LVCMOS reset (
RESET ) and control (C1)
inputs. The INSSTU32S869 operates with a
differential clock input (CK and CK ). Input data
is registered at the crossing point of rising CK and
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falling CK . In a typical Registered DIMM
application, the outputs can each drive up to 18
SDRAM input loads.
The INSSTU32S869 supports low-power
standby mode. When RESET is low, the clock,
data, and reference voltage (V
REF
) input receivers
are disabled, and floating inputs are allowed for
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these signals. Additionally, all registers are reset,
and all outputs except
PTYERR1
are forced low.
The RESET and C1 inputs must always be held
at valid logic levels. Asynchronous transitions of
RESET are supported. RESET must be held
low during power-up to ensure well-defined
outputs from the register before a stable clock has
been supplied.
The INSSTU32S869 continually evaluates
parity of the data inputs and a parity input bit
generated by the memory controller (PARIN1).
Valid parity is defined as even, i.e. an even number
of ones among the data inputs and PARIN1. The
DIMM-dependent DCKE,
DCS
, DODT, and
data. The PPO1 signal of the first device, which is
generated two cycles after the corresponding data
input and one cycle after the corresponding
PARIN1, then drives PARIN1 of the second
device. The second device completes evaluation
of the full data word by evaluating its PARIN1 bit
(PPO1 of the first device) together with the
remaining data bits. The
PTYERR1
signal from
the second device is generated three cycles after
the data input and two cycles after the parity bit
from the memory controller is applied to PARIN1
of the first device. If a parity error occurs, the
PTYERR1
from the second device goes low and
latches low for two clock cycles, or until RESET
is driven low. N consecutive parity errors will
cause
PTYERR1
to stay low for N+1 clock
cycles.
The device supports low-power active
operation by monitoring the
DCS
and
CSR
inputs. The Qn, PPO, and
PTYERR1
outputs
are prevented from changing states when both
CSR
inputs are omitted from parity evaluation.
The DIMM-dependent data inputs D1, D4, and
D7 are also omitted from parity evaluation.
When the INSSTU32S869 is used as a
single device (C1 held low), parity is evaluated on
the PARIN1 input, which arrives one cycle after
the corresponding input data. The partial-parity-
out (PPO1) and parity error (
PTYERR1
) output
signals are generated two cycles after the
corresponding data inputs and one cycle after the
corresponding PARIN1 input.
When the INSSTU32S869 is used in pairs
the first device has C1 held low, and the second
device has C1 held high. Parity is first evaluated
on the PARIN1 input of the first device, which
arrives one cycle after the corresponding input
DCS
and
CSR
are high. If either
DCS
or
CSR
is low, then these outputs will function
normally. The RESET input has priority over the
DCS
and
CSR
controls. When asserted, it
forces Qn and PPO to low and
PTYERR1
to
high.
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Part Number Selection Table
This register is certified for use on the Raw Cards listed below as defined in PC2-3200/PC2-4200 Registered
DIMM Design Specification. It is guaranteed to produce over/undershoots less than indicated in the table
below to comply with DDR2 SDRAM Over/Undershoot requirements under worst-case DRAM loading
conditions (Min or Max), and over all DIMM operating conditions in Table 5 of the specification.
Inphi Product
Part Number
INSSTU32S869
INSSTUA32S869
INSSTUB32869
RDIMM
Speed Bin
Module
W
400, 533
Max
Overshoot
0.5V
Min
Overshoot
0.5V
W
W
400, 533, 667
400, 533, 667, 800
0.5V
0.5V
0.5V
0.5V
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Terminal Functions
Terminal Name
Description
Electrical
Characteristics
Ground
1.8 V nominal
GND
V
DD
V
REF
CK
CK
Ground
Power supply
Input reference voltage
Clock input, latches data on rising edge
Complementary clock input
Configuration control input – First (or only) register if low, second
register if high
Asynchronous reset input: resets registers and disables data, clock,
and V
REF
input receivers
Chip select enable – If
CSR
and
DCS
inputs are both high, then
0.9 V nominal
SSTL_18
Differential input
SSTL_18
Differential input
LVCMOS input
LVCMOS input
C1
RESET
CSR
D1-D14
1
output switching is disabled. If either
CSR
or
DCS
input
is low, the D1-D14
1
inputs will be latched on every rising edge of
the clock.
Data inputs - clocked in on the crossing of rising edge of CK and
falling edge of
CK
Chip select input – This signal initiates DRAM address/command
decodes. If
CSR
and
DCS
inputs are both high, then D1-D14
1
output switching is disabled. If either
CSR
or
DCS
input is low, the
D1-D14
1
inputs will be latched on every rising edge of the clock.
SSTL_18 input
D1-D14
1
SSTL_18 inputs
DCS
SSTL_18 input
DODT, DCKE
PARIN1
Q1A-Q14A
2
Q1B-Q14B
2
QCSA
,
QCSB
Outputs of register bits that are not suspended by the
CSR
and
DCS
control inputs.
Parity input – arrives one or two clock cycles after the
corresponding data input
SSTL_18 inputs
SSTL_18 input
SSTL_18 outputs
SSTL_18 outputs
SSTL_18 outputs
Open-drain
output
LVCMOS output
May connect to
PCB
Data outputs that are suspended by the
CSR
and
DCS
control
inputs
Data outputs that are not suspended by the
CSR
and
DCS
control
inputs
Data outputs that are not suspended by the
CSR
and
DCS
control
inputs
Parity error output – generated two or three clock cycles after the
corresponding data input
Partial parity output - indicates parity of inputs D1 – D14
QODTA, DODTB,
QCKEA, QCKEB
PTYERR1
PPO1
NC
Notes:
1
2
No connect. Ball present but no internal connection to the die.
Does not include data inputs D1, D4, and D7
Does not include data outputs Q1A, Q4A, Q7A, Q1B, Q4B, and Q7B
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Block Diagrams
Logic diagram
C1
VREF
LSP0 internal node (CS Active)
PARITY
GENERATOR
AND
CHECKER
2
PARIN1
D
PPO1
PTYERR1
R
11
1
D1
D
Q1A
R
Q1B
D14
D
Q14A
R
DCS
D
Q14B
QCSA
R
CSR
QCSB
DCKE
D
QCKEA
R
DODT
QCKEB
D
QODTA
R
RESET
CK
CK
Notes:
1
QODTB
Does not include data inputs D1, D4, and D7
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