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SS9018I

Description
Transistor
CategoryDiscrete semiconductor    The transistor   
File Size174KB,1 Pages
ManufacturerJCET
Websitehttp://www.cj-elec.com/

Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); ​​QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

 

 

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SS9018I Overview

Transistor

SS9018I Parametric

Parameter NameAttribute value
MakerJCET
package instruction,
Reach Compliance Codeunknown

SS9018I Preview

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JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD
TO-92 Plastic-Encapsulate Transistors
SS9018
TRANSISTOR (NPN)
TO-92
1.EMITTER
FEA TURES
High Current Gain Bandwidth Product
2.BASE
MAXIMUM RATINGS (T
a
=25℃ unless otherwise noted)
Symbol
V
CBO
V
CEO
V
EBO
I
C
P
C
R
θJA
T
j
T
stg
Parameter
Collector-Base Voltage
Collector-Emitter Voltage
Emitter-Base Voltage
Collector Current -Continuous
Collector Power Dissipation
Junction Temperature
Storage Temperature
Value
Units
25
18
4
50
0.4
150
V
V
V
mA
W
3.COLLECTOR
Thermal Resistance from Junction to Ambient 312.5
℃/W
-55-150
ELECTRICAL CHARACTERISTICS (T
a
=25℃ unless otherwise specified)
Parameter
Collector-base breakdown voltage
Collector-emitter breakdown voltage
Emitter-base breakdown voltage
Collector cut-off current
Collector cut-off current
Emitter cut-off current
DC current gain
Collector-emitter saturation voltage
Base-emitter saturation voltage
Transition frequency
Symbol
V
(BR)CBO
V
(BR)CEO
V
(BR)EBO
I
CBO
I
CEO
I
EBO
h
FE
V
CE(sat)
V
BE(sat)
Test conditions
I
C
= 100μA, I
E
=0
I
C
= 0.1mA, I
B
=0
I
E
= 100μA, I
C
=0
V
CB
= 20V, I
E
=0
V
CE
=15V,I
B
=0
V
EB
=3V, I
C
=0
V
CE
=5V, I
C
= 1mA
I
C
=10mA, I
B
=1mA
I
C
=10mA,I
B
=1mA
V
CE
=5 V, I
C
=5mA
f =400MHz
1.2
28
Min
25
18
4
0.1
0.1
0.1
270
0.5
1.42
V
V
GHz
Typ
Max
Unit
V
V
V
μA
μA
μA
f
T
CLASSIFICATION OF h
FE
Rank
Ra nge
D
28-45
E
39-60
F
54-80
G
72-108
H
97-146
I
132-198
J
180-270
A,May,2011
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