3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q80C
GD25Q80C
DATASHEET
1
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q80C
Contents
1.
2.
3.
4.
5.
6.
7.
FEATURES
................................................................................................................................................................ 4
GENERAL DESCRIPTION
...................................................................................................................................... 5
MEMORY ORGANIZATION
.................................................................................................................................... 7
DEVICE OPERATION
.............................................................................................................................................. 8
DATA PROTECTION
................................................................................................................................................ 9
STATUS REGISTER
............................................................................................................................................... 11
COMMANDS DESCRIPTION
............................................................................................................................... 13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
7.13.
7.14.
7.15.
7.16.
7.17.
7.18.
7.19.
7.20.
7.21.
7.22.
7.23.
7.24.
7.25.
7.26.
7.27.
7.28.
7.29.
7.30.
7.31.
7.32.
W
RITE
E
NABLE
(WREN) (06H) ......................................................................................................................... 16
W
RITE
D
ISABLE
(WRDI) (04H) ......................................................................................................................... 16
R
EAD
S
TATUS
R
EGISTER
(RDSR) (05H
OR
35H) ............................................................................................... 16
W
RITE
S
TATUS
R
EGISTER
(WRSR) (01H).......................................................................................................... 17
W
RITE
E
NABLE FOR
V
OLATILE
S
TATUS
R
EGISTER
(50H) .................................................................................. 17
R
EAD
D
ATA
B
YTES
(READ) (03H) .................................................................................................................... 18
R
EAD
D
ATA
B
YTES AT
H
IGHER
S
PEED
(F
AST
R
EAD
) (0BH) .............................................................................. 18
D
UAL
O
UTPUT
F
AST
R
EAD
(3BH) ...................................................................................................................... 19
Q
UAD
O
UTPUT
F
AST
R
EAD
(6BH) ..................................................................................................................... 19
D
UAL
I/O F
AST
R
EAD
(BBH) ............................................................................................................................. 20
Q
UAD
I/O F
AST
R
EAD
(EBH) ............................................................................................................................. 22
Q
UAD
I/O W
ORD
F
AST
R
EAD
(E7H) .................................................................................................................. 23
S
ET
B
URST WITH
W
RAP
(77H) ........................................................................................................................... 24
P
AGE
P
ROGRAM
(PP) (02H) ............................................................................................................................... 24
Q
UAD
P
AGE
P
ROGRAM
(32H)............................................................................................................................. 25
S
ECTOR
E
RASE
(SE) (20H) ................................................................................................................................. 26
32KB B
LOCK
E
RASE
(BE) (52H) ....................................................................................................................... 27
64KB B
LOCK
E
RASE
(BE) (D8H) ...................................................................................................................... 27
C
HIP
E
RASE
(CE) (60/C7H) ............................................................................................................................... 28
D
EEP
P
OWER
-D
OWN
(DP) (B9H) ....................................................................................................................... 28
R
ELEASE FROM
D
EEP
P
OWER
-D
OWN OR
H
IGH
P
ERFORMANCE
M
ODE AND
R
EAD
D
EVICE
ID (RDI) (ABH)...... 29
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (REMS) (90H)........................................................................................ 30
R
EAD
I
DENTIFICATION
(RDID) (9FH) ................................................................................................................ 31
H
IGH
P
ERFORMANCE
M
ODE
(HPM) (A3H) ........................................................................................................ 31
C
ONTINUOUS
R
EAD
M
ODE
R
ESET
(CRMR) (FFH) ............................................................................................ 32
P
ROGRAM
/E
RASE
S
USPEND
(PES) (75H) ........................................................................................................... 33
P
ROGRAM
/E
RASE
R
ESUME
(PER) (7AH) ........................................................................................................... 33
E
RASE
S
ECURITY
R
EGISTERS
(44H) ................................................................................................................... 34
P
ROGRAM
S
ECURITY
R
EGISTERS
(42H).............................................................................................................. 34
R
EAD
S
ECURITY
R
EGISTERS
(48H)..................................................................................................................... 35
E
NABLE
R
ESET
(66H)
AND
R
ESET
(99H) ............................................................................................................ 36
R
EAD
S
ERIAL
F
LASH
D
ISCOVERABLE
P
ARAMETER
(5AH) ................................................................................. 36
2
3.3V Uniform Sector
Dual and Quad Serial Flash
8.
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
9.
10.
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
11.
GD25Q80C
ELECTRICAL CHARACTERISTICS
................................................................................................................... 41
POWER-ON TIMING ....................................................................................................................................... 41
INITIAL DELIVERY STATE ........................................................................................................................... 41
ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 41
CAPACITANCE MEASUREMENT CONDITIONS ....................................................................................... 42
DC CHARACTERISTICS................................................................................................................................. 43
AC CHARACTERISTICS................................................................................................................................. 44
ORDERING INFORMATION
................................................................................................................................. 47
PACKAGE INFORMATION
............................................................................................................................... 48
P
ACKAGE
SOP8 150MIL ................................................................................................................................... 48
P
ACKAGE
SOP8 208MIL ................................................................................................................................... 49
P
ACKAGE
DIP8 300MIL .................................................................................................................................... 50
P
ACKAGE
USON8 (3*2
MM
,
THICKNESS
0.45
MM
) .............................................................................................. 51
P
ACKAGE
USON8 (3*4
MM
) ............................................................................................................................... 52
P
ACKAGE
USON8 (4*4
MM
,
THICKNESS
0.45
MM
) .............................................................................................. 53
REVISION HISTORY
.......................................................................................................................................... 54
3
3.3V Uniform Sector
Dual and Quad Serial Flash
1. FEATURES
◆
GD25Q80C
8M-bit Serial Flash
-1024K-byte
-256 bytes per programmable page
◆
Program/Erase Speed
-Page Program time: 0.6ms typical
-Sector Erase time: 45ms typical
-Block Erase time: 0.15/0.25s typical
◆
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆
-Chip Erase time: 4s typical
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64k-byte
◆
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-Quad I/O Data transfer up to 480Mbits/s
◆
Low Power Consumption
-20mA maximum active current
-1uA maximum power down current
◆
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top or Bottom, Sector or Block selection
◆
Advanced Security Features
(1)
-128-Bit Unique ID for each device
-4*256-Byte Security Registers With OTP Locks
-Discoverable parameters(SFDP) register
◆
Cycling endurance
-Minimum 100,000 Program/Erase Cycles
◆
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
◆
Data retention
-20-year data retention typical
Note: 1.Please contact GigaDevice for details.
4
3.3V Uniform Sector
Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
GD25Q80C
The GD25Q80C (8M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
CONNECTION DIAGRAM
CS#
SO
WP#
VSS
1
2
Top View
3
4
6
5
SCLK
SI
WP# 3
VSS 4
8–LEAD USON
8
7
VCC
HOLD#
CS#
SO
1
2
Top View
6 SCLK
5
SI
8
7
VCC
HOLD#
8–LEAD SOP/VSOP/DIP
PIN DESCRIPTION
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
I/O
I
I/O
I/O
I
I/O
I/O
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5