GD25LT256E
GD25LT256E
DATASHEET
1
GD25LT256E
Contents
1.
2.
3.
4.
FEATURES
.........................................................................................................................................................5
GENERAL DESCRIPTION
................................................................................................................................6
MEMORY ORGANIZATION
...............................................................................................................................9
DEVICE OPERATION
...................................................................................................................................... 10
4.1.
4.2.
4.3.
4.4.
4.5.
5.
6.
SPI M
ODE
............................................................................................................................................................ 10
QPI M
ODE
............................................................................................................................................................ 10
Q
UAD
DTR M
ODE
................................................................................................................................................. 10
ECC F
UNCTION
...................................................................................................................................................... 10
RESET F
UNCTION
.................................................................................................................................................. 11
DATA PROTECTION
........................................................................................................................................ 12
DATA INTEGRITY CHECK
.............................................................................................................................. 14
6.1.
6.2.
6.3.
ECC (E
RROR
C
HECKING AND
C
ORRECTING
) ................................................................................................................. 14
ECS# (E
RROR CORRECTED
S
IGNAL
) P
IN
...................................................................................................................... 15
P
ARITY
C
HECK
(CRC) .............................................................................................................................................. 15
7.
STATUS AND EXTENDED ADTRESS REGISTERS
.................................................................................... 16
7.1.
7.2.
7.3.
S
TATUS
R
EGISTER
................................................................................................................................................... 16
F
LAG
S
TATUS
R
EGISTER
........................................................................................................................................... 17
E
XTENDED
A
DDRESS
R
EGISTER
.................................................................................................................................. 18
8.
INTERNAL CONFIGURATION REGISTER
................................................................................................... 20
8.1.
8.2.
8.3.
8.4.
N
ONVOLATILE
C
ONFIGURATION
R
EGISTER
................................................................................................................... 20
V
OLATILE
C
ONFIGURATION
R
EGISTER
......................................................................................................................... 22
S
UPPORTED
C
LOCK
F
REQUENCIES
.............................................................................................................................. 26
D
ATA
S
EQUENCE
W
RAPS BY
D
ENSITY
......................................................................................................................... 27
9.
COMMANDS DESCRIPTION
.......................................................................................................................... 28
9.1.
9.2.
9.3.
9.4.
9.5.
9.6.
9.7.
9.8.
9.9.
9.10.
9.11.
E
NABLE
4-B
YTE
M
ODE
(B7H) .................................................................................................................................. 33
D
ISABLE
4-B
YTE
M
ODE
(E9H) .................................................................................................................................. 33
W
RITE
E
NABLE
(WREN) (06H) ................................................................................................................................ 34
W
RITE
D
ISABLE
(WRDI) (04H) ................................................................................................................................ 34
W
RITE
E
NABLE FOR
V
OLATILE
S
TATUS
R
EGISTER
(50H) ................................................................................................. 35
W
RITE
S
TATUS
R
EGISTER
(WRSR) (01H) ................................................................................................................... 35
W
RITE
E
XTENDED
A
DDRESS
R
EGISTER
(C5H)............................................................................................................... 36
W
RITE
N
ONVOLATILE
/V
OLATILE
C
ONFIGURATION
R
EGISTER
(B1H/81H) ......................................................................... 37
R
EAD
S
TATUS
R
EGISTER OR
F
LAG
R
EGISTER
(05H)........................................................................................................ 38
R
EAD
F
LAG
S
TATUS
R
EGISTER OR
F
LAG
R
EGISTER
(70H) ................................................................................................ 39
R
EAD
N
ONVOLATILE
/V
OLATILE
C
ONFIGURATION
R
EGISTER
(B5H/85H) ........................................................................... 39
2
GD25LT256E
9.12.
9.13.
9.14.
9.15.
9.16.
9.17.
9.18.
9.19.
9.20.
9.21.
9.22.
9.23.
9.24.
9.25.
9.26.
9.27.
9.28.
9.29.
9.30.
9.31.
9.32.
9.33.
9.34.
9.35.
9.36.
9.37.
9.38.
9.39.
9.40.
10.
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
11.
11.1.
12.
12.1.
12.2.
R
EAD
E
XTENDED
A
DDRESS
R
EGISTER
(C8H) ................................................................................................................ 40
R
EAD
D
ATA
B
YTES
(03H/13H) ................................................................................................................................ 41
R
EAD
D
ATA
B
YTES AT
H
IGHER
S
PEED
(0BH/0CH) ........................................................................................................ 42
Q
UAD
O
UTPUT
F
AST
R
EAD
(6BH/6CH) ..................................................................................................................... 43
Q
UAD
I/O F
AST
R
EAD
(EBH/ECH) ........................................................................................................................... 44
Q
UAD
I/O DTR R
EAD
(EDH/EEH) ........................................................................................................................... 46
P
AGE
P
ROGRAM
(PP) (02H/12H) ............................................................................................................................ 48
Q
UAD
P
AGE
P
ROGRAM
(32H/34H) .......................................................................................................................... 49
E
XTEND
Q
UAD
P
AGE
P
ROGRAM
(C2H/3EH) .............................................................................................................. 51
S
ECTOR
E
RASE
(SE) (20H/21H) ............................................................................................................................... 52
32KB B
LOCK
E
RASE
(BE) (52H/5CH) ....................................................................................................................... 53
64KB B
LOCK
E
RASE
(BE) (D8H/DCH) ...................................................................................................................... 54
C
HIP
E
RASE
(CE) (60/C7H) ..................................................................................................................................... 55
C
LEAR
SR F
LAGS
(30H) ........................................................................................................................................... 56
E
NABLE
QPI (38H) ................................................................................................................................................ 56
D
ISABLE
QPI (FFH) ................................................................................................................................................ 56
D
EEP
P
OWER
-D
OWN
(DP) (B9H) ............................................................................................................................. 57
R
ELEASE FROM
D
EEP
P
OWER
-D
OWN
(ABH) ............................................................................................................... 57
R
EAD
U
NIQUE
ID (4BH) .......................................................................................................................................... 58
R
EAD
I
DENTIFICATION
(RDID) (9FH/9EH) ................................................................................................................. 59
P
ROGRAM
/E
RASE
S
USPEND
(PES) (75H) ................................................................................................................... 60
P
ROGRAM
/E
RASE
R
ESUME
(PER) (7AH) ................................................................................................................... 61
E
RASE
S
ECURITY
R
EGISTERS
(44H) ............................................................................................................................ 62
P
ROGRAM
S
ECURITY
R
EGISTERS
(42H) ....................................................................................................................... 63
R
EAD
S
ECURITY
R
EGISTERS
(48H) ............................................................................................................................. 64
I
NDIVIDUAL
B
LOCK
/S
ECTOR
L
OCK
(36H)/U
NLOCK
(39H)/R
EAD
(3DH) ........................................................................... 66
G
LOBAL
B
LOCK
/S
ECTOR
L
OCK
(7EH)
OR
U
NLOCK
(98H) ............................................................................................... 68
E
NABLE
R
ESET
(66H)
AND
R
ESET
(99H) ..................................................................................................................... 69
R
EAD
S
ERIAL
F
LASH
D
ISCOVERABLE
P
ARAMETER
(5AH)................................................................................................. 70
ELECTRICAL CHARACTERISTICS
.......................................................................................................... 72
POWER-ON TIMING ........................................................................................................................................... 72
INITIAL DELIVERY STATE ..................................................................................................................................... 72
ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 72
CAPACITANCE MEASUREMENT CONDITIONS .................................................................................................... 73
DC CHARACTERISTICS......................................................................................................................................... 74
AC CHARACTERISTICS ......................................................................................................................................... 75
ORDERING INFORMATION
........................................................................................................................ 79
V
ALID
P
ART
N
UMBERS
............................................................................................................................................ 80
PACKAGE INFORMATION
......................................................................................................................... 81
P
ACKAGE
SOP16 300
MIL
....................................................................................................................................... 81
P
ACKAGE
TFBGA-24BALL (5
X
5
BALL ARRAY
) ............................................................................................................. 82
3
GD25LT256E
13.
REVISION HISTORY
.................................................................................................................................... 83
4
GD25LT256E
1. FEATURES
◆
256M-bit Serial Flash
- 32M-Byte
- 256 Bytes per programmable page
◆
Fast Program/Erase Speed
- Page Program time: 0.4ms typical
- Sector Erase time: 30ms typical
- Block Erase time: 0.1/0.2s typical
◆
Standard, Quad SPI, DTR,QPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, RESET#
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3, RESET#
- QPI: SCLK, CS#, IO0, IO1, IO2, IO3, RESET#
- SPI DTR (Double Transfer Rate) Read
- 3 or 4-Byte Address Mode
◆
- Chip Erase time: 50s typical
Flexible Architecture
- Sector of 4K-Byte
- Block of 32/64K-Byte
- Erase/Program Suspend/Resume
◆
◆
High Speed Clock Frequency
- 200MHz for fast read with 30PF load
- Quad I/O Data transfer up to 664Mbits/s
- QPI Mode Data transfer up to 664Mbits/s
- DTR Quad I/O Data transfer up to 1600Mbits/s with DQS
Low Power Consumption
- 25uA typical stand-by current
- 5uA typical power down current
◆
Advanced Security Features
- 128-bit Unique ID
◆
Allows XIP(execute in place)operation
- High speed Read reduce overall XiP instruction fetch time
- Continuous Read with Wrap further reduce data latency to
fill up SoC cache
◆
- 4K-Byte Security Registers With OTP Lock
Single Power Supply Voltage
- Full voltage range:1.65~2.0V
◆
◆
Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# Pin
- Advanced Sector Protection
- Top or Bottom selection
Endurance and Data Retention
- Minimum 100,000 Program/Erase Cycles
- 20-year data retention typical
◆
Package Information
- SOP16 300mil
◆
Data
Integrity Check
- TFBGA-24ball (5x5 Ball Array)
- On-chip ECC (1-bit correction every 8-Byte)
(1)
- CRC detects accidental changes to raw data
Note:
1.
When ECC is enabled, it is required to program minimum one or multiple aligned 8-Byte granularities. Every aligned 8-
Byte granularity should only be programmed once before Erase to ensure correct ECC operations.
5