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CJ3407

Description
Drain-source voltage (Vdss): 30V Continuous drain current (Id) (at 25°C): 4.1A Gate-source threshold voltage: 3V @ 250uA Drain-source on-resistance: 60mΩ @ 4.1A, 10V Maximum power dissipation ( Ta=25°C): 350mW Type: P channel P channel, -30V, -4.1A, 60mΩ@-10V
CategoryDiscrete semiconductor    MOS (field effect tube)   
File Size173KB,3 Pages
ManufacturerJCET
Websitehttp://www.cj-elec.com/

Jiangsu Changdian Technology Co., Ltd. focuses on semiconductor packaging and testing business, providing customers at home and abroad with a full range of solutions such as chip testing, packaging design, packaging testing, etc. The company was successfully listed on the Shanghai Main Board in 2003, becoming the first semiconductor packaging and testing listed company in China. It now has a national enterprise technology center and a postdoctoral research workstation. It is a national key high-tech enterprise, a supporting unit of the National Engineering Laboratory for High-density Integrated Circuits, and the chairman unit of the Integrated Circuit Packaging Technology Innovation Strategic Alliance.

Discrete devices: diodes (switching diodes, Schottky diodes (Schottky rectifiers), voltage regulator diodes, Pin diodes, TVS diodes, rectifier diodes, fast recovery diodes); transistors (Darlington tubes, digital transistors, MOSFETs); thyristors: silicon-controlled rectifiers, triacs; composite tubes: transistors + field-effect tubes, dual transistors, dual digital transistors, digital transistors + transistors, transistors + diodes, field-effect tubes + diodes, dual field-effect tubes. Voltage regulator circuit; energy-saving lamp charger switch tube

Lead frame: TO series (TO); SOD series (SOD); SOT series (TSOT, SOT); FBP series (WBFBP); QFN series (QFNWB, DFNWB, DFNFC, QFNFC); ​​QFP series (LQFP: PQFP: PLCC: TQFP); SIP series (SIP, HSIP, FSIP); SOP series (SOP, HSOP, SSOP, MSOP, HTSOP, TSSOP); DIP series (DIP, FDIP, SDIP); PDFN series; PQFN series; MIS series (MISFC, MISWB)

Nine core technologies: Through Silicon Via (TSV) packaging technology; SiP RF packaging technology; wafer-level 3D rewiring packaging process technology; copper bump interconnection technology; high-density FC-BGA packaging and testing technology (Flip Chip BGA); multi-turn array four-sided pinless packaging and testing technology; package body 3D stacking technology; 50μm or less ultra-thin chip 3D stacking packaging technology; MEMS multi-chip packaging technology; MIS packaging technology (pre-encapsulated interconnection system); BGA packaging technology, etc.

 

 

Download Datasheet Parametric View All

CJ3407 Overview

Drain-source voltage (Vdss): 30V Continuous drain current (Id) (at 25°C): 4.1A Gate-source threshold voltage: 3V @ 250uA Drain-source on-resistance: 60mΩ @ 4.1A, 10V Maximum power dissipation ( Ta=25°C): 350mW Type: P channel P channel, -30V, -4.1A, 60mΩ@-10V

CJ3407 Parametric

Parameter NameAttribute value
Drain-source voltage (Vdss)30V
Continuous drain current (Id) at 25°C4.1A
Gate-source threshold voltage3V @ 250uA
Drain-source on-resistance60mΩ @ 4.1A,10V
Maximum power dissipation (Ta=25°C)350mW
typeP channel

CJ3407 Preview

Download Datasheet
JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD
SOT-23 Plastic-Encapsulate MOSFETS
CJ3407
P-Channel Enhancement Mode Field Effect Transistor
SOT-23
General Description
The CJ3407 uses advanced trench technology to provide excellent
R
DS(on)
with low gate charge. This device is suitable for use as a load
switch or in PWM applications.
MARKING: 3407
1. GATE
2. SOURCE
3. DRAIN
Maximum ratings (T
a
=25℃ unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Power Dissipation
Thermal Resistance from Junction to Ambient
Junction Temperature
Storage Temperature
Symbol
V
DS
V
GS
I
D
P
D
R
θJA
T
J
T
stg
Value
-30
±20
-4.1
350
357
150
-55~+150
Unit
V
V
A
mW
℃/W
A,Dec,2010
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