3PA1030
Complete 10-Bit, 50MSPS, CMOS Analog-to-Digital Converter
FEATURES
PRODUCT DESCRIPTION
The 3PA1030 is a monolithic, single supply, 10-Bit, 50 MSPS
analog-to-digital converter with an on-chip sample-and-hold
amplifier and voltage reference. The 3PA1030 uses multi-stage
differential pipeline architecture at 50 MSPS data rates and
guarantees no missing codes over the full operating temperature
range.
The input of the 3PA1030 has been designed to ease the
development of both imaging and communications systems. The
user can select a variety of input ranges and offsets and can drive
the input either single-ended or differentially.
The sample and hold (SHA) amplifier is equally suited for both
multiplexed systems that switch full-scale voltage levels in
successive channels and sampling single channel inputs at
frequencies up to and beyond the Nyquist rate. AC coupled input
signals can be shifted to a predetermined level, with an on-board
3PEAK proprietary clamp circuit. The dynamic performance is
excellent.
CMOS 10-Bit, 50 MSPS Sampling A/D Converter
Configurable Input: Single-Ended or Differential
Differential Nonlinearity: 0.3 LSB
Three State Outputs
Out of Range Indicator
Built In Clamp Function (DC Restore)
Adjustable On Chip Voltage Reference
IF Under sampling to 135 MHz
Power Dissipation: 84 mW (3 V Supply)
Power Down (Sleep) Mode: 10
W
Operation Between +2.7 V and +5.5V Supply
Green, 28-Lead TSSOP Package
Pin Compatible with THS1030, AD9200 and AD876 Family
PRODUCT HIGHLIGHTS
Low Power:
The 3PA1030 speed is 50MSPS but only
consumes 84 mW on a 3 V supply. In sleep mode, power is
reduced to 10
W.
Pin Compatible with THS1030/TLC876/AD9200/AD876:
The 3PA1030 allows older designs to migrate to higher speed
and lower supply voltages.
100 MHz On-board Sample-and-Hold:
The versatile SHA
input can be configured for either single ended or differential
inputs.
Out-of-Range Indicator:
The OTR output bit indicates when
the input signal is beyond the 3PA1030’s input range.
Built-In Clamp Function:
Allows dc restoration of video
signals.
The 3PA1030 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy
and temperature drift requirements of the application.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an
overflow condition which can be used with the most significant
bit to determine low or high overflow.
The 3PA1030 can operate with a supply ranging from +2.7 V to
+5.5 V, ideally suiting it for low power operation in high speed
applications.
The 3PA1030 is specified over the industrial (–40°C to +85°C)
temperature range.
Figure 1. Functional Block Diagram
REV-1.2
www.3peakic.com.cn
-1-
3PA1030
Complete 10-Bit, 50MSPS, CMOS Analog-to-Digital Converter
PIN CONFIGURATION
AGND
DVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OVR
DGND
AVDD
AIN
VREF
REFBS
REFBF
MODE
REFTF
REFTS
CLAMPIN
CLAMP
REFSENSE
STBY
OE
CLK
3PA1030
28-Lead TSSOP
Figure 2. Pin Location
TSSOP
Pin. No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
AGND
DVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OVR
DGND
CLK
OE
STBY
REFSENSE
CLAMP
CLAMPIN
REFTS
REFTF
MODE
REFBF
REFBS
VREF
AIN
AVDD
Description
Analog Ground
Digital Driver Supply
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9 Most Significant Bit
Out of Range Indicator
Digital Ground
Clock Input
HI: High Impedance State. LO: Normal Operation
HI: Power Down Mode. LO: Normal Operation
Reference Select
HI: Enable Clamp Mode. LO: No Clamp
Clamp Reference Input
Top reference
Top Reference Decoupling
Mode select
Bottom Reference Decoupling
Bottom reference
Internal Reference Output
Analog Input
Analog Supply
ORDERING GUIDE
Model
3PA1030
Temperature Range
–40°C to+85°C
Package
28-Lead TSSOP
Transport Media, Quantity
Tape and Reel, 2500
ABSOLUTE MAXIMUM RATINGS *
Parameter
AVDD
DRVDD
AVSS
AVDD
MODE
CLK
Digital Outputs
AIN
VREF
REFSENSE
With Respect to
AVSS
DRVSS
DRVSS
DRVDD
AVSS
AVSS
DRVSS
AVSS
AVSS
AVSS
Min
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Max
6.5
6.5
0.3
6.5
AVDD+0.3
AVDD+0.3
DRVDD+0.3
AVDD+0.3
AVDD+0.3
AVDD+0.3
Units
V
V
V
V
V
V
V
V
V
V
REV-1.2
www.3peakic.com.cn
-2-
3PA1030
Complete 10-Bit, 50MSPS, CMOS Analog-to-Digital Converter
REFTF,REFTB
REFTS,REFBS
Junction Temperature
Storage Temperature
Lead Temperature10sec
AVSS
AVSS
–0.3
–0.3
–65
AVDD+0.3
AVDD+0.3
150
150
300
V
V
°C
°C
°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may effect device reliability.
ELECTRICAL CHARACTERISTICS
AVDD = +3 V, DRVDD = +3 V, F
S
= 50 MHz (50% Duty Cycle), 2 V Input Span from 0 V to 2 V, Internal Reference, T
MIN
to T
MAX
Unless Otherwise
Noted)
Rating
Min
Typ
10
50
±0.3
±0.9
±0.2
±1.6
0.75
0.25
1
REFSENSE = AVDD
Between REFTF & REFBF
10
1
2*(REFT-
REFB)
2
4
2
300
5
0.5
±10
1
2.7
2.7
AVDD = 3 V,
AVDD = DVDD = 3 V,
CLOCK = AVSS, STBY =
AVDD
PSRR
28
84
10
1
±1.0
±2.0
±1.2
±5.0
1.5
0.5
2
Max
Parameter
RESOLUTION
CONVERSION RATE
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Gain Error
REFERENCE VOLTAGES
Top Reference Voltage
Bottom Reference Voltage
Differential Reference Voltage
Reference Input Resistance
ANALOG INPUT
Input Voltage Range
Input Capacitance
Aperture Delay
Aperture Uncertainty (Jitter)
Input Bandwidth (–3 dB)
DC Leakage Current
INTERNAL REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2 V Mode)
POWER SUPPLY
Operating Voltage
Supply Current
Power Consumption
Power-Down
Gain Error Power Supply Rejection
Symbol
Condition
Units
Bits
MHz
LSB
LSB
%FSR
%FSR
V
V
V p-p
kΩ
kΩ
F
S
DNL
INL
E
ZS
E
FS
REFTS
REFBS
AIN
C
IN
t
AP
t
AJ
BW
Switched
0
V
pF
ns
ps
MHz
A
V
mV
V
V
V
mA
mW
W
% FS
V
IN
> 80mV
VREF
VREF
AVDD
DRVDD
IAVDD
P
D
REFSENSE = VREF
REFSENSE = GND
±25
5.5
5.5
REV-1.2
www.3peakic.com.cn
-3-
3PA1030
Complete 10-Bit, 50MSPS, CMOS Analog-to-Digital Converter
Parameter
DYNAMIC PERFORMANCE (AIN = 0.5 dBFS)
Signal-to-Noise and Distortion
Effective Bits
Signal-to-Noise
Total Harmonic Distortion
Spurious Free Dynamic Range
Differential Phase
Differential Gain
DIGITAL INPUTS
High Input Voltage
Low Input Voltage
DIGITAL OUTPUTS
High-Z Leakage
Data Valid Delay
Data Enable Delay
Data High-Z Delay
CLOCKING
Clock Pulse-width High
Clock Pulse-width Low
Pipeline Latency
CLAMP
Clamp Error Voltage
Clamp Pulse-width
E
OC
t
CPW
CLAMPIN = +0.5V to +2.0V,
R
IN
= 10 Ω
C
IN
= 1 μF (Period = 63.5 μs)
±60
2
±80
mV
μs
t
CH
t
CL
9.5
9.5
3
ns
ns
Cycles
V
IH
V
IL
I
OZ
t
OD
t
DEN
t
DHZ
Output = GND to V
DD
C
L
= 20 pF
2.4
0.3
–10
25
25
13
10
V
V
μA
ns
ns
ns
SNR
THD
SFDR
DP
DG
SINAD
f = 3.58 MHz
f = 16 MHz
f = 3.58 MHz
f = 16 MHz
f = 3.58 MHz
f = 16 MHz
f = 3.58 MHz
f = 16 MHz
f = 3.58 MHz
f = 16 MHz
NTSC 40 IRE Mod Ramp
52.5
8.4
53
56.5
48.6
9
7.8
57.5
53.1
–60
–58
–66
–61
0.2
0.08
dB
dB
Bits
Bits
dB
dB
dB
dB
dB
dB
Degree
%
Symbol
Condition
Rating
Units
–56
–56
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual code
from a line drawn from “zero” through “full scale.” The point used as
“zero” occurs 1/2 LSB before the first code transition. “Full scale” is
defined as a level 1 1/2 LSB beyond the last code transition. The
deviation is measured from the center of each particular code to the
true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart.
DNL is the deviation from this ideal value. It is often specified in
terms of the resolution for which no missing codes (NMC) are
guaranteed.
Offset Error
Transition should occur at a level 1 LSB above “zero.” Offset is
defined as the deviation of the actual first code transition from that
point.
Gain Error
The first code transition should occur for an analog value 1 LSB
above nominal negative full scale. The last transition should occur
for an analog value 1 LSB below the nominal positive full scale.
Gain Error is the deviation of the actual difference between first and
last code transitions and the ideal difference between the first and
last code transitions.
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and the
associated output data being made available. New output data is
provided every rising edge.
REV-1.2
www.3peakic.com.cn
-4-
3PA1030
Complete 10-Bit, 50MSPS, CMOS Analog-to-Digital Converter
TYPICAL CHARACTERIZATION CURVES
AVDD = +3 V, DRVDD = +3 V, F
S
= 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input Span from 0.5 V to 2.5 V, External Reference, Unless
Otherwise Noted.
Figure 3. Typical DNL
Figure 6. SINAD vs. Input Frequency
Figure 4. Typical INL
Figure 7. THD vs. Input Frequency
Figure 5. SNR vs. Input Frequency
Figure 8. THD vs. Clock Frequency
REV-1.2
www.3peakic.com.cn
-5-
MicroPython Open Source section
京公网安备 11010802033920号
EEWORLD
