2EZ6.8~2EZ51
SILICON ZENER DIODES
VOLTAGE
FEATURES
• Plastic package has Underwriters Laboratory Flammability
Classification 94V-O
• High temperature soldering : 260°C /10 seconds at terminals
• Lead free in compliance with EU RoHS 2011/65/EU directive
0.300(7.6)
0.230(5.8)
1.0(25.4)MIN.
6.8 to 51 Volt
POWER
2 Watt
0.034(0.86)
0.028(0.71)
• Low inductance
• Case: JEDEC DO-15, Molded plastic over passivated junction
• Terminals: Solder plated, solderable per MIL-STD-750, Method 2026
• Polarity: Color band denotes cathode end
• Standard packing: 52mm tape
• Weight: 0.014 ounce, 0.0397 gram
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS
Ratings at 25°C ambient temperature unless otherwise specified.
Parameter
Max Steady State Power Dissipation @T
L
<80
O
C (Note A)
Derate above T
A
=25
O
C
Peak Forward Surge Current 8.3ms single half sine-wave
soperimposed on rated load
Thermal resistance Junction to Ambient
Junction to Lead
Operating Junction and Storage Temperature Range
S ymb o l
P
D
I
FSM
R
JA
R
JL
T
J
, T
STG
1.0(25.4)MIN.
MECHANICAL DATA
0.140(3.6)
0.104(2.6)
Va lue
2
15
60
32
-55 to + 150
Uni t
Watts
Amps
o
C/W
o
C
NOTE:
A.Mounted on infinite heat sink with L=2mm
B.Measured on 8.3ms, and single half sine-wave or equivalent square wave, duty cycle=4 pulses per minute maximum
February 21,2014-REV.04
PAGE . 1
2EZ6.8~2EZ51
2.5
500
P
D
, Maximum Power Dissipation (W)
P
PK
, PEAK SURGE POWER (WATTS)
2
L=2mm
250
100
100
50
25
15
10
5
0.1 0.20.3 0.5
RECTAN GULAR
NON - REPETIT IVE
T
J
=25
O
C PRIOR
TOINTIA L PULSE
1.5
1
L
L
0.5
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
1
2 3
5
10 20 30 50
100
T
L
, Lead Temperature (
℃
)
P.W.PULSE WIDTH(ms)
Fig.1 Power Temperature Derating Curve
FIGURE 2. MAXIMUM SURGE POWER
FIGURE 3. TYPICAL THERMAL RESPONSEL,
APPLICATION NOTE:
Since the actual voltage available from a given zener diode is temperature dependent, it is necessary to determinejunction
temperature under any set of operating conditions in order to calculate its value. The following procedure is recommended:
Lead Temperature, T
L
, should be determined from:
T
L
=
q
L
A
P
D
+ T
A
O
q
L
A
is the lead-to-ambient thermal resistance ( C/W) and Pd is the power dissipation. The value for
q
L
A
will vary and depends
on the device mounting method.
q
L
A
is generally 30-40
O
C/W for the various clips and tie points in common use and for printed
circuit board wiring.
The temperature of the lead can also be measured using a thermocouple placed on the lead as close as possible to the tie point.
The thermal mass connected to the tie point is normally large enough so that it will not significantly respond to heat surges
generated in the diode as a result of pulsed operation once steady-state conditions are achieved. Using the measured value of
TL, the junction temperature may be determined by:
T
J
= T
L
+
D
T
JL
D
T
JL
is the increase in junction temperature above the lead temperature and may be found from Figure 3 for a train of power pulses
or from Figure 10 for dc power.
D
T
JL
=
q
J
L
P
D
For worst-case design, using expected limits of I
Z
, limits of P
D
and the extremes of T
J
(
D
T
J
) may be estimated. Changes in voltage,
V
Z
, can then be found from:
D
V =
q
V
Z
D
T
J
q
V
Z
, the zener voltage temperature coefficient, is found from Figures 5 and 6.
Under high power-pulse operation, the zener voltage will vary with time and may also be affected significantly by the zener resistance.
For best regulation, keep current excursions as low as possible.
Data of Figure 3 should not be used to compute surge capa-bility. Surge limitations are given in Figure 2. They are lower than would
be expected by considering only junction temperature, as current crowding effects cause temperatures to be extremely high in small
spots resulting in device degradation should the limits of Figure 2 be exceeded.
February 21,2014-REV.04
PAGE . 3
Parametric
View All
Domestic Chip Exchange
京公网安备 11010802033920号
EEWORLD
