pulse width modulation circuit

Pulse width modulation circuit, first analyze the circuit. The pulse is 3uS/5V, so Q4 is normally closed. Instantaneous conduction of 3uS during operation. So Q5 should be normally on and transiently off. This seems to be completely different from what xbtxbt said. So preliminary analysis suggests that 1: the circuit principle is wrong. Possibility 2: The circuit diagram is wrong. Possibility 3: As shown in Yang Zhenren's picture, xbtxbt misrepresented the input signal.
Inferred from the direction of diode D21: Possibility 3 is true.
Assume first that possibility 3 holds.
In normal state, R21 and C21 are charged, turning Q4 on, the voltage at point C is 0.3~0.4V, point D is divided by R23 and R22, and C22 is charged through R23 to Udc. Q5 is turned on. The Q5-S voltage should be slightly less than UD.
When the signal appears, D21 and R21 discharge C21 together, Q4 turns off quickly, and the voltage at point C increases. At this time, C22 bootstraps, and the voltage at point D increases accordingly. The voltage of Q5-G rises >200V, and the voltage of Q5-S rises rapidly.
After the signal ends. R21 and C21 charge, causing Q4 to conduct, the voltage at points C and D drops, and Q5-S drops. Return to normalcy.
No matter how the component parameters are modified, 0V voltage will not appear at the Q5-S terminal. It should change between UD~VCC time.

The changes are as follows:
1. Because C21, R21, and D21 form the front stage of a simple monostable circuit, C21 should be as small as possible, which is conducive to rapid discharge and plays a decisive role in the slope of the output pulse front edge. R21 should be larger to extend the charging time and make the output monostable effect obvious. This part of the circuit plays the role of the first stage delay.
2. Connect a 100Ω resistor in series before Q4-B, otherwise the voltage on C21 can only reach 0.7V at most.
3. When Q4 is on in the normal state, the voltage across C22 is equal to the divided voltage across R22. C22 discharges through R22 during bootstrapping. To increase the delay effect, the C22 capacitor and R22 resistance should be increased. However, due to the limitation of signal source frequency, the charging time of R23 to C22 is limited. Therefore, C22 and R23 cannot be too large. Calculate carefully. Increasing R22 will cause the partial pressure to be too high, affecting the output of Q5-S.
4. At the same time, since it is a bootstrap circuit, D22 has no effect. During bootstrap, there is no current path under C22.
This circuit has certain feasibility when used in a 30VDC circuit, but the consequences are unpredictable when used in a 200VDC circuit. C22 charging and discharging speed and resistor power are issues. Calculate strictly.