Serial communication bus in automobile

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More and more electronic systems require more reliable interconnection solutions, and LIN bus is becoming an emerging standard for automotive serial communication.

Three issues that are very important to automakers are fuel efficiency, reliability, and cost. As more and more electronic systems are added to car designs, the issues become more complex. Each of these subsystems adds cost and requires a good interconnection strategy, which presents more challenges for automotive designers.

Figure 1: Mixed-signal array partitioned into PSoC logic blocks

Figure 2 LIN bus can be used as the second level of a two-level bus structure

Simply wiring these new electronic systems together is not a viable solution. One approach to solving the problem is to use a serial communication bus to replace the wiring between electronic modules. Using a serial communication bus reduces the number of wires and connections in the wiring harness, thereby reducing costs and improving reliability. It also improves fuel efficiency due to the lighter design.

The two most widely used digital bus standards in automotive applications are CAN ( control area network ) bus and J1850 . Each bus is suitable for specific applications in the automotive market based on factors such as speed, bus latency and cost. A new bus standard called LIN ( local interconnect network ) can complement the original more mature bus structure and cover applications where the original bus is not good at.

The LIN bus was developed by the LIN Alliance , a non-profit organization of automotive, software and semiconductor manufacturers . The LIN bus is a Class A bus, that is, it is a low-speed bus. The maximum communication rate of the LIN bus is 20 Kb/s . It also provides guaranteed latency, that is, communication from a specific node to another node in the network is guaranteed to be completed within the specified time.

The biggest advantage of the LIN bus is its low implementation cost. The cost of a LIN bus node is only about half of that of a similar CAN bus node.

It should be pointed out that the development of LIN bus is not to compete with other bus structures, but to form a complementary relationship with other buses. Specifically, LIN bus can be used as the second level in a two-level bus structure, in which CAN bus can be used as the first-level trunk bus. In this structure, some CAN bus nodes can also be used as gateways, that is, as the master nodes of the local LIN bus.

The LIN bus protocol is based on the universal UART byte interface, so the implementation methods are rich and flexible. The LIN protocol adopts a master / slave communication mechanism. The bus includes a master node and one or more slave nodes. In addition to driving the transmission of all messages, the master node also completes all arbitration and conflict management work. This further simplifies the slave node, thereby reducing its cost.

All communications on the bus are carried out in the form of messages, which have a certain format, called a message frame. The message frame consists of a header information field and a response field. The header information is further divided into several fields. The first is the synchronization interrupt field, which consists of 13 ' 0 ' bits and at least one ' 1 ' bit, used to mark the beginning of the frame. Then there is the synchronization field consisting of a series of alternating ' 1 ' and ' 0 ', which allows each slave node to synchronize to the bit rate set by the master node; finally, there is the flag field, which marks the required message and the length of the response field.

Only the master node can initiate the message transmission process, which is achieved by sending a header field to all nodes. The flag field in the header field tells all slave nodes in the network what response to make. Possible responses include: receiving byte data from the response field; sending byte data in the response field; or doing nothing. Each slave node analyzes the header information field and must be ready to send or receive data in the response field of the frame.

When implementing the LIN bus using a traditional microcontroller (MCU) with a built-in UART , encoding and decoding at the byte level is simple and efficient. However, the work of creating and interpreting the entire message frame requires more resources that are not usually available in the MCU .

For example, the synchronization field is used to determine the bit rate, which is something that each slave node must do at the beginning of each message. Implementing this function on a traditional MCU requires a hardware timer and software polling, which places a heavy burden on the processor. Another example is that all nodes need to detect several error conditions, which can occur in each bit and therefore can consume a lot of processing power. In general, all of these features of the LIN bus protocol either require a lot of CPU overhead or require dedicated hardware resources that only a few MCUs can provide.

PSoC Opportunities and Advantages

Cypress 's programmable system-on-chip (PSoC) devices offer a third option. The purpose of developing this series of products is to replace traditional fixed-function MCUs . Each PSoC device is a mixed-signal array with an integrated microcontroller. The programmable analog and digital circuits that make up these mixed-signal arrays are divided into logic modules called PSoC blocks ( see Figure 1) . Each module can perform a series of functions, including many standard peripheral functions. Therefore, in the application, a "perfect" set of peripherals can be configured. The digital PSoC module can be used to complete all the hardware functions required for the LIN bus interface, freeing the CPU from these tasks.

In addition to reducing CPU overhead, it also reduces the digital resources used by the LIN bus function. More resources can be used to complete other functions. The dynamic reconfiguration feature of this structure allows different configurations of the device to be dynamically selected to complete different functions during the device operation.

Dynamic reconfiguration can greatly facilitate LIN bus designs based on PSoC. Since LIN bus transmission has three distinct phases: header transmission / reception, data transmission, and data reception, the PSoC device can reconfigure its digital block resources at each phase to implement the different functions required by the LIN bus protocol. This is possible because the information that determines the chip configuration is stored in RAM- based registers, and data is transferred from flash memory at startup to configure the chip to an initial state. Therefore, user code can change the values in these registers at any time, thereby changing the configuration of PSoC resources.

The code memory required to implement the LIN bus protocol is very small ( about 1.5 Kbytes if PSoC is used as a slave node and about 1Kbyte if used as a master node ) . Cypress 's PSoC devices can provide up to 16K of flash memory, so most of the program space can be left for the application. The CPU overhead required for driver management is also very low, requiring only about 10% of the CPU cycles, and most of the hardware PSoC modules (5/8) can be left for the main application.

Cypress has designed a LIN bus reference design board that can be used to evaluate PSoC - based LIN bus node designs. This reference design is part of a complete design kit (CY3220LINBUS-RD) . Software to implement LIN bus communication can be downloaded from www.cypressmicro.com . No licensing fees are required.

More and more electronic systems require more reliable interconnection solutions, and LIN bus is becoming an emerging standard for automotive serial communication.

Three issues that are very important to automakers are fuel efficiency, reliability, and cost. As more and more electronic systems are added to car designs, the issues become more complex. Each of these subsystems adds cost and requires a good interconnection strategy, which presents more challenges for automotive designers.

Figure 1: Mixed-signal array partitioned into PSoC logic blocks

Figure 2 LIN bus can be used as the second level of a two-level bus structure

Simply wiring these new electronic systems together is not a viable solution. One approach to solving the problem is to use a serial communication bus to replace the wiring between electronic modules. Using a serial communication bus reduces the number of wires and connections in the wiring harness, thereby reducing costs and improving reliability. It also improves fuel efficiency due to the lighter design.

The two most widely used digital bus standards in automotive applications are CAN ( control area network ) bus and J1850 . Each bus is suitable for specific applications in the automotive market based on factors such as speed, bus latency and cost. A new bus standard called LIN ( local interconnect network ) can complement the original more mature bus structure and cover applications where the original bus is not good at.

The LIN bus was developed by the LIN Alliance , a non-profit organization of automotive, software and semiconductor manufacturers . The LIN bus is a Class A bus, that is, it is a low-speed bus. The maximum communication rate of the LIN bus is 20 Kb/s . It also provides guaranteed latency, that is, communication from a specific node to another node in the network is guaranteed to be completed within the specified time.

The biggest advantage of the LIN bus is its low implementation cost. The cost of a LIN bus node is only about half of that of a similar CAN bus node.

It should be pointed out that the development of LIN bus is not to compete with other bus structures, but to form a complementary relationship with other buses. Specifically, LIN bus can be used as the second level in a two-level bus structure, in which CAN bus can be used as the first-level trunk bus. In this structure, some CAN bus nodes can also be used as gateways, that is, as the master nodes of the local LIN bus.

The LIN bus protocol is based on the universal UART byte interface, so the implementation methods are rich and flexible. The LIN protocol adopts a master / slave communication mechanism. The bus includes a master node and one or more slave nodes. In addition to driving the transmission of all messages, the master node also completes all arbitration and conflict management work. This further simplifies the slave node, thereby reducing its cost.

All communications on the bus are carried out in the form of messages, which have a certain format, called a message frame. The message frame consists of a header information field and a response field. The header information is further divided into several fields. The first is the synchronization interrupt field, which consists of 13 ' 0 ' bits and at least one ' 1 ' bit, used to mark the beginning of the frame. Then there is the synchronization field consisting of a series of alternating ' 1 ' and ' 0 ', which allows each slave node to synchronize to the bit rate set by the master node; finally, there is the flag field, which marks the required message and the length of the response field.

Only the master node can initiate the message transmission process, which is achieved by sending a header field to all nodes. The flag field in the header field tells all slave nodes in the network what response to make. Possible responses include: receiving byte data from the response field; sending byte data in the response field; or doing nothing. Each slave node analyzes the header information field and must be ready to send or receive data in the response field of the frame.

When implementing the LIN bus using a traditional microcontroller (MCU) with a built-in UART , encoding and decoding at the byte level is simple and efficient. However, the work of creating and interpreting the entire message frame requires more resources that are not usually available in the MCU .

For example, the synchronization field is used to determine the bit rate, which is something that each slave node must do at the beginning of each message. Implementing this function on a traditional MCU requires a hardware timer and software polling, which places a heavy burden on the processor. Another example is that all nodes need to detect several error conditions, which can occur in each bit and therefore can consume a lot of processing power. In general, all of these features of the LIN bus protocol either require a lot of CPU overhead or require dedicated hardware resources that only a few MCUs can provide.

PSoC Opportunities and Advantages

Cypress 's programmable system-on-chip (PSoC) devices offer a third option. The purpose of developing this series of products is to replace traditional fixed-function MCUs . Each PSoC device is a mixed-signal array with an integrated microcontroller. The programmable analog and digital circuits that make up these mixed-signal arrays are divided into logic modules called PSoC blocks ( see Figure 1) . Each module can perform a series of functions, including many standard peripheral functions. Therefore, in the application, a "perfect" set of peripherals can be configured. The digital PSoC module can be used to complete all the hardware functions required for the LIN bus interface, freeing the CPU from these tasks.

In addition to reducing CPU overhead, it also reduces the digital resources used by the LIN bus function. More resources can be used to complete other functions. The dynamic reconfiguration feature of this structure allows different configurations of the device to be dynamically selected to complete different functions during the device operation.

Dynamic reconfiguration can greatly facilitate LIN bus designs based on PSoC. Since LIN bus transmission has three distinct phases: header transmission / reception, data transmission, and data reception, the PSoC device can reconfigure its digital block resources at each phase to implement the different functions required by the LIN bus protocol. This is possible because the information that determines the chip configuration is stored in RAM- based registers, and data is transferred from flash memory at startup to configure the chip to an initial state. Therefore, user code can change the values in these registers at any time, thereby changing the configuration of PSoC resources.

The code memory required to implement the LIN bus protocol is very small ( about 1.5 Kbytes if PSoC is used as a slave node and about 1Kbyte if used as a master node ) . Cypress 's PSoC devices can provide up to 16K of flash memory, so most of the program space can be left for the application. The CPU overhead required for driver management is also very low, requiring only about 10% of the CPU cycles, and most of the hardware PSoC modules (5/8) can be left for the main application.

Cypress has designed a LIN bus reference design board that can be used to evaluate PSoC - based LIN bus node designs. This reference design is part of a complete design kit (CY3220LINBUS-RD) . Software to implement LIN bus communication can be downloaded from www.cypressmicro.com . No licensing fees are required.

More and more electronic systems require more reliable interconnection solutions, and LIN bus is becoming an emerging standard for automotive serial communication.

Three issues that are very important to automakers are fuel efficiency, reliability, and cost. As more and more electronic systems are added to car designs, the issues become more complex. Each of these subsystems adds cost and requires a good interconnection strategy, which presents more challenges for automotive designers.

Figure 1: Mixed-signal array partitioned into PSoC logic blocks

Figure 2 LIN bus can be used as the second level of a two-level bus structure

Simply wiring these new electronic systems together is not a viable solution. One approach to solving the problem is to use a serial communication bus to replace the wiring between electronic modules. Using a serial communication bus reduces the number of wires and connections in the wiring harness, thereby reducing costs and improving reliability. It also improves fuel efficiency due to the lighter design.

The two most widely used digital bus standards in automotive applications are CAN ( control area network ) bus and J1850 . Each bus is suitable for specific applications in the automotive market based on factors such as speed, bus latency and cost. A new bus standard called LIN ( local interconnect network ) can complement the original more mature bus structure and cover applications where the original bus is not good at.

The LIN bus was developed by the LIN Alliance , a non-profit organization of automotive, software and semiconductor manufacturers . The LIN bus is a Class A bus, that is, it is a low-speed bus. The maximum communication rate of the LIN bus is 20 Kb/s . It also provides guaranteed latency, that is, communication from a specific node to another node in the network is guaranteed to be completed within the specified time.

The biggest advantage of the LIN bus is its low implementation cost. The cost of a LIN bus node is only about half of that of a similar CAN bus node.

It should be pointed out that the development of LIN bus is not to compete with other bus structures, but to form a complementary relationship with other buses. Specifically, LIN bus can be used as the second level in a two-level bus structure, in which CAN bus can be used as the first-level trunk bus. In this structure, some CAN bus nodes can also be used as gateways, that is, as the master nodes of the local LIN bus.

The LIN bus protocol is based on the universal UART byte interface, so the implementation methods are rich and flexible. The LIN protocol adopts a master / slave communication mechanism. The bus includes a master node and one or more slave nodes. In addition to driving the transmission of all messages, the master node also completes all arbitration and conflict management work. This further simplifies the slave node, thereby reducing its cost.

All communications on the bus are carried out in the form of messages, which have a certain format, called a message frame. The message frame consists of a header information field and a response field. The header information is further divided into several fields. The first is the synchronization interrupt field, which consists of 13 ' 0 ' bits and at least one ' 1 ' bit, used to mark the beginning of the frame. Then there is the synchronization field consisting of a series of alternating ' 1 ' and ' 0 ', which allows each slave node to synchronize to the bit rate set by the master node; finally, there is the flag field, which marks the required message and the length of the response field.

Only the master node can initiate the message transmission process, which is achieved by sending a header field to all nodes. The flag field in the header field tells all slave nodes in the network what response to make. Possible responses include: receiving byte data from the response field; sending byte data in the response field; or doing nothing. Each slave node analyzes the header information field and must be ready to send or receive data in the response field of the frame.

When implementing the LIN bus using a traditional microcontroller (MCU) with a built-in UART , encoding and decoding at the byte level is simple and efficient. However, the work of creating and interpreting the entire message frame requires more resources that are not usually available in the MCU .

For example, the synchronization field is used to determine the bit rate, which is something that each slave node must do at the beginning of each message. Implementing this function on a traditional MCU requires a hardware timer and software polling, which places a heavy burden on the processor. Another example is that all nodes need to detect several error conditions, which can occur in each bit and therefore can consume a lot of processing power. In general, all of these features of the LIN bus protocol either require a lot of CPU overhead or require dedicated hardware resources that only a few MCUs can provide.

PSoC Opportunities and Advantages

Cypress 's programmable system-on-chip (PSoC) devices offer a third option. The purpose of developing this series of products is to replace traditional fixed-function MCUs . Each PSoC device is a mixed-signal array with an integrated microcontroller. The programmable analog and digital circuits that make up these mixed-signal arrays are divided into logic modules called PSoC blocks ( see Figure 1) . Each module can perform a series of functions, including many standard peripheral functions. Therefore, in the application, a "perfect" set of peripherals can be configured. The digital PSoC module can be used to complete all the hardware functions required for the LIN bus interface, freeing the CPU from these tasks.

In addition to reducing CPU overhead, it also reduces the digital resources used by the LIN bus function. More resources can be used to complete other functions. The dynamic reconfiguration feature of this structure allows different configurations of the device to be dynamically selected to complete different functions during the device operation.

Dynamic reconfiguration can greatly facilitate LIN bus designs based on PSoC. Since LIN bus transmission has three distinct phases: header transmission / reception, data transmission, and data reception, the PSoC device can reconfigure its digital block resources at each phase to implement the different functions required by the LIN bus protocol. This is possible because the information that determines the chip configuration is stored in RAM- based registers, and data is transferred from flash memory at startup to configure the chip to an initial state. Therefore, user code can change the values in these registers at any time, thereby changing the configuration of PSoC resources.

The code memory required to implement the LIN bus protocol is very small ( about 1.5 Kbytes if PSoC is used as a slave node and about 1Kbyte if used as a master node ) . Cypress 's PSoC devices can provide up to 16K of flash memory, so most of the program space can be left for the application. The CPU overhead required for driver management is also very low, requiring only about 10% of the CPU cycles, and most of the hardware PSoC modules (5/8) can be left for the main application.

Cypress has designed a LIN bus reference design board that can be used to evaluate PSoC - based LIN bus node designs. This reference design is part of a complete design kit (CY3220LINBUS-RD) .