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Please help compare the PCB layout of a boost DCDC [Copy link]

This post was last edited by flyriz on 2018-3-5 09:38 Hello everyone, as the title says, a 12V to 48V Roman]DCDC boostcircuit, the chip model isXL6019, the following threePCBlayouts, which one is better? What is the reason for the bad place? Please give some advice, thank you! Here is the schematic diagram: I will give screenshots of the PCB layout later. Layout 1: Layout 2: Layout 3:

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The second one is better.  Details Published on 2018-3-9 15:31
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Do not use external links. Many websites prohibit external links. The circuit diagram must be uploaded to this site.
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It's OK, please take the time to look at it. Thank you!  Details Published on 2018-3-5 09:38
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chunyang posted on 2018-3-2 20:16 Do not use external links. Many websites prohibit external links. The circuit diagram must be uploaded to this site.
It's OK. Please take the time to look at it. Thank you!
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Your design is not good, the problem is mainly the sampling loop. Let's talk about the design principles of this part. First, the output sampling loop should be as close to the power chip as possible. Second, the shorter the loop connection, the better. At the same time, do not use vias in the loop. To achieve this, you must also pay attention to the layout of the output loop to meet the requirements of short sampling connections. The reason for doing this is to reduce the impact of distributed parameters on sampling accuracy, in order to achieve relatively lower ripple parameters.
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However, there is also a saying that the sampling loop should be connected from the output through the filter capacitor and then to the sampling point of the chip. In this case, are these two statements in conflict?  Details Published on 2018-3-6 16:34
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chunyang posted on 2018-3-5 16:31 Your designs are not good. The problem is mainly the sampling circuit. Let's talk about the design principles of this part. First, the output sampling circuit should be as close to the power supply as possible...
But there is also a saying that the sampling circuit should be connected from the output to the sampling point of the chip after passing through the filter capacitor. In this case, are these two statements in conflict?
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The two are not in conflict. The filtering circuit has similar requirements, requiring the impedance of the output circuit to be as small as possible, and then sampling from the main filter capacitor.  Details Published on 2018-3-6 23:54
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flyriz posted on 2018-3-6 16:34 But there is also a saying that: the sampling loop should be connected to the sampling point of the chip after passing through the filter capacitor from the output. In this case, are these two statements...
The two are not in conflict. The filter circuit has similar requirements, requiring the impedance of the output circuit to be as small as possible, and then sampling from the main filter capacitor.
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The feedback sampling pin of this chip is sensitive to PCB wiring. For example, the FB of XL6019 is the output voltage sampling pin. The wiring should be as short as possible and away from noise sources such as inductors or diodes to reduce the space affected by interference.
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When the entire copper is laid on the back side of a high-power power supply circuit, it is important to pay attention to heat conduction. The feedback of FB may change due to the increase in heat, resulting in unstable output voltage. It is best to use a sampling resistor with a small temperature effect. Metal film resistors are relatively stable.
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The second one is better.
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