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Summary of the usage of DSP series software waiting [Copy link]

DSP has a fast instruction cycle, so it is necessary to add a wait when accessing slow memory or peripherals. Waiting is divided into hardware waiting and software waiting, and the waiting of each series is not exactly the same. 1) For C2000 series: The hardware wait signal is READY, and there is no wait when it is high. The software wait is determined by the WSGR register, and up to 7 waits can be added. Among them, the program memory, data memory and I/O can be set separately. 2) For C3x series: The hardware wait signal is /RDY, and there is no wait when it is low. The software wait is determined by SWW and WTCNY in the bus control register, and up to 7 waits can be added, but the wait is not segmented and is valid in all spaces except within the chip. 3) For the C5000 series: The hardware wait signal is READY, and there is no wait when the level is high. The software wait is determined by the SWWCR and SWWSR registers, and up to 14 waits can be added. Among them, the program memory, control program memory, data memory and I/O can be set separately. 4) For the C6000 series (limited to asynchronous memory or peripherals): The hardware wait signal is ARDY, and there is no wait when the level is high. The software wait is determined by the external memory interface control register, and the timing of the bus accessing the external memory or device can be set, which can facilitate the synchronous and asynchronous memory or peripheral interfaces.

This post is from DSP and ARM Processors
 

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