Four addressing modes of MSP430F15X/16X DMA

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Four addressing modes of MSP430F15X/16X DMA [Copy link]

The DMA module of the MSP430F16x series microcontroller has the following features: Data transfer does not require CPU intervention and is completely managed by the DMA controller. Data can be transferred within the entire address space, and block transfer can reach 65536 bytes; it can improve the data throughput of on-chip peripherals and achieve high-speed transmission, and only 2 MCLKs are required for each word or byte transmission; it reduces system power consumption, and the CPU can be in ultra-low power mode without waking up even when on-chip peripherals are inputting or outputting data; Byte and word data can be mixed and transferred: DMA transfer can be byte to byte, word to word, byte to word, or word to byte. When word to byte is transferred, only the lower byte in the word can be transferred. When transferring from byte to word, the lower byte of the word is transferred, and the high byte is automatically cleared; four transfer addressing modes: fixed address to fixed address, fixed address to block address, block address to fixed address, and block address to block address; flexible triggering mode: edge or level triggering. Single, block or burst block transfer mode: Each time a DMA operation is triggered, data of different sizes can be transferred as needed. The four addressing modes of DMA are shown in the figure below: DMA controller module: 3 independent transmission channels: channel 0, channel 1 and channel 2. Each channel has a source address register, a destination address register, a transfer data length register and a control register. The trigger request of each channel can be enabled and disabled separately; Configurable channel priority: Priority arbitration module, the priority of the transmission channel can be adjusted, and priority arbitration is performed on channels with trigger requests at the same time to determine which channel has the highest priority. The DMA controller of MSP430 can use fixed priority or circular priority. Program command control module, before each DMA channel starts to transfer, the CPU must be programmed to give relevant commands and mode controls to determine the type of DMA channel transfer; Configurable transfer triggers: trigger source selection module, DMAREQ (software trigger), Timer_ACCR2 output, Timer_BCCR2 output, I2C data receive ready, I2C data send ready, USART receive send data, DAC12 module DAC12IFG, ADC12 module ADC12IFGx, DMAxIFG, DMAE0 external trigger source. And it also has the ability to expand the trigger source.